dchvs/li-mt9m021
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base: dchvs:3f911eb3f39d3836453a68a834ae8447350bbab3
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dchvs:master
dchvs:feature/resolution-1280x960
dchvs:jetpack-4.4.1
dchvs:hotfix/fix-low-framerate
dchvs:jetpack-4.2.2
dchvs:v0.2.6
dchvs:v0.2.5
dchvs:v0.2.4
dchvs:v0.2.3
dchvs:v0.2.2
dchvs:v0.2.1
dchvs:v0.2.0
dchvs:v0.1.0
..
compare: dchvs:d8cb8d7139e6c38608ad1faf8e220c6389a2d242
Branches Tags
dchvs:master
dchvs:feature/resolution-1280x960
dchvs:jetpack-4.4.1
dchvs:hotfix/fix-low-framerate
dchvs:jetpack-4.2.2
dchvs:v0.2.6
dchvs:v0.2.5
dchvs:v0.2.4
dchvs:v0.2.3
dchvs:v0.2.2
dchvs:v0.2.1
dchvs:v0.2.0
dchvs:v0.1.0

No commits in common. "3f911eb3f39d3836453a68a834ae8447350bbab3" and "d8cb8d7139e6c38608ad1faf8e220c6389a2d242" have entirely different histories.
3f911eb3f3 ... d8cb8d7139

2 changed files with 22 additions and 27 deletions
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8
hardware/nvidia-spiri/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-tx2-spiri-camera.dtsi
View File

@ -102,7 +102,7 @@ i2c8 = "/i2c@31e0000";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "100000";
max_gain_val = "796000";
max_gain_val = "797000";
step_gain_val = "1";
default_gain = "100000";
min_hdr_ratio = "1";
@ -116,7 +116,7 @@ i2c8 = "/i2c@31e0000";
min_exp_time = "500"; // us
max_exp_time = "16000"; // us
step_exp_time = "1";
default_exp_time = "12000"; // us
default_exp_time = "8000"; // us
};
ports {
#address-cells = <0x1>;
@ -189,7 +189,7 @@ i2c8 = "/i2c@31e0000";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "100000";
max_gain_val = "796000";
max_gain_val = "797000";
step_gain_val = "1";
default_gain = "100000";
min_hdr_ratio = "1";
@ -203,7 +203,7 @@ i2c8 = "/i2c@31e0000";
min_exp_time = "500"; // us
max_exp_time = "16000"; // us
step_exp_time = "1";
default_exp_time = "12000"; // us
default_exp_time = "8000"; // us
};
ports {
#address-cells = <0x1>;

41
kernel/nvidia-spiri/drivers/media/i2c/mt9m021.c
View File

@ -135,8 +135,8 @@
#define MT9M021_ANALOG_GAIN_SHIFT 4
#define MT9M021_ANALOG_GAIN_MASK 0x0030
#define MT9M021_GLOBAL_GAIN_MIN 100000
#define MT9M021_GLOBAL_GAIN_MAX 796000
#define MT9M021_GLOBAL_GAIN_MIN 100
#define MT9M021_GLOBAL_GAIN_MAX 797
#define MT9M021_GLOBAL_GAIN_DEF 100
#define MT9M021_COARSE_INT_TIME_MIN 0x0001
@ -424,9 +424,7 @@ static int mt9m021_set_gain(struct tegracam_device *tc_dev, s64 val)
*
* min_gain_val = 100.000
* max_gain_val = 797.000
* gain_factor = 3125
*
* gain maps to range 32 - 255
* step_gain_val = 3125
*/
gain = val / 3125;
@ -439,14 +437,14 @@ static int mt9m021_set_gain(struct tegracam_device *tc_dev, s64 val)
((gain_mul << MT9M021_ANALOG_GAIN_SHIFT) &
MT9M021_ANALOG_GAIN_MASK);
err = mt9m021_write_reg16(s_data, MT9M021_DIGITAL_TEST, reg16);
// msleep(10);
msleep(10);
if (err)
goto exit;
/* Update global gain */
err =
mt9m021_write_reg16(s_data, MT9M021_GLOBAL_GAIN, gain);
// msleep(10);
msleep(10);
if (err)
goto exit;
err =
@ -492,8 +490,8 @@ static int mt9m021_set_frame_rate(struct tegracam_device *tc_dev, s64 val)
/* Calculate frame-length */
frame_length = mode->signal_properties.pixel_clock.val *
mode->control_properties.framerate_factor /
mode->image_properties.line_length / val;
mode->control_properties.framerate_factor /
mode->image_properties.line_length / val;
err = mt9m021_set_frame_length(priv, frame_length);
if (err)
@ -520,7 +518,7 @@ static int mt9m021_set_coarse_time(struct mt9m021 *priv, s64 val)
err = mt9m021_write_reg16(s_data, MT9M021_COARSE_INT_TIME_CB, val);
if (err)
return err;
// msleep(30);
msleep(30);
return 0;
}
@ -535,14 +533,14 @@ static int mt9m021_set_exposure(struct tegracam_device *tc_dev, s64 val)
u64 coarse_time;
int err = 0;
dev_dbg(dev, "Setting Exposure Time to : %lld", val);
dev_dbg(dev, "Setting Exposure Time to : %lld", val);
coarse_time =
val * mode->signal_properties.pixel_clock.val /
mode->image_properties.line_length /
mode->control_properties.exposure_factor;
err = mt9m021_set_coarse_time(priv, coarse_time);
err = mt9m021_set_coarse_time(priv, coarse_time);
if (err)
goto exit;
@ -571,7 +569,7 @@ static int mt9m021_set_analog_gain(struct tegracam_device *tc_dev, s64 val)
((val << MT9M021_ANALOG_GAIN_SHIFT) &
MT9M021_ANALOG_GAIN_MASK);
err = mt9m021_write_reg16(s_data, MT9M021_DIGITAL_TEST, reg16);
// msleep(30);
msleep(30);
if (err)
goto exit;
@ -627,7 +625,7 @@ static int mt9m021_set_digital_gain(struct tegracam_device *tc_dev, s64 val,
err = mt9m021_write_reg16(s_data, gain_cb_reg, val);
if (err)
goto exit;
// msleep(30);
msleep(30);
return 0;
@ -650,7 +648,7 @@ static int mt9m021_set_test_pattern(struct tegracam_device *tc_dev, s32 val)
else
err = mt9m021_write_reg16(s_data, MT9M021_TEST_PATTERN,
val);
// msleep(30);
msleep(30);
if (err)
goto exit;
@ -963,15 +961,13 @@ static int mt9m021_col_correction(struct mt9m021 *priv)
if (ret < 0)
return ret;
// msleep(200);
// usleep(200);
msleep(200);
/* Enable Streaming */
ret = mt9m021_write_table(priv, mode_table[MT9M021_MODE_START_STREAM]);
if (ret < 0)
return ret;
// msleep(200);
// usleep(200);
msleep(200);
/* Disable Streaming */
ret = mt9m021_write_table(priv, mode_table[MT9M021_MODE_STOP_STREAM]);
@ -982,8 +978,7 @@ static int mt9m021_col_correction(struct mt9m021 *priv)
ret = mt9m021_write_reg16(s_data, MT9M021_COLUMN_CORRECTION, 0xE007);
if (ret < 0)
return ret;
// msleep(200);
// usleep(200);
msleep(200);
return ret;
}
@ -1013,7 +1008,7 @@ static int mt9m021_set_mode(struct tegracam_device *tc_dev)
dev_err(dev, "%s: Failed to set pll setup\n", __func__);
return ret;
}
msleep(100);
msleep(100);
ret = mt9m021_col_correction(priv);
if (ret < 0) {
@ -1098,7 +1093,7 @@ static int mt9m021_get_trigger_mode(struct mt9m021 *priv)
}
err =
of_property_read_string(node, "trigger_mode", &priv->trigger_mode);
of_property_read_string(node, "trigger_mode", &priv->trigger_mode);
if (err == -EINVAL) {
dev_warn(&client->dev, "trigger_mode not in device tree\n");
*(&priv->trigger_mode) = "master";