forked from rrcarlosr/Jetpack
78 lines
1.8 KiB
C
78 lines
1.8 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _P3450_PORG_H
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#define _P3450_PORG_H
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#include <linux/sizes.h>
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#include "tegra210-common.h"
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/* High-level configuration options */
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#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-PORG"
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/* Board-specific serial config */
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#define CONFIG_TEGRA_ENABLE_UARTA
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/* I2C */
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#define CONFIG_SYS_I2C_TEGRA
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#define CONFIG_SYS_VI_I2C_TEGRA
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_TEGRA_MMC
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/* Only MMC1/PXE/DHCP for now, add USB back in later when supported */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na)
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/* Environment at end of QSPI, in the VER partition */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_MAX_HZ 48000000
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#define CONFIG_ENV_SECT_SIZE SZ_4K
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/* 4MB flash, environment located as high as possible */
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#define CONFIG_ENV_OFFSET (SZ_4M - OFFSET_OF_UBOOT_ENV)
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/* SPI */
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 24000000
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#define CONFIG_SPI_FLASH_SIZE (4 << 20)
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/* USB2.0 Host support */
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_TEGRA
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#define CONFIG_PREBOOT
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#define BOARD_EXTRA_ENV_SETTINGS \
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"preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
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"load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
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"source ${scriptaddr}; " \
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"fi\0"
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/* General networking support */
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#include "tegra-common-usb-gadget.h"
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#include "tegra-common-post.h"
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/* Crystal is 38.4MHz. clk_m runs at half that rate */
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#define COUNTER_FREQUENCY 19200000
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/* Turn SDMMC1 off in early init on Porg/Nano */
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#define CONFIG_DISABLE_SDMMC1_EARLY
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#endif /* _P3450_PORG_H */
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