forked from rrcarlosr/Jetpack
131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*
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* drivers/platform/tegra/wdt-recovery.c
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*
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* Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/suspend.h>
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#include <linux/resource.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/clk/tegra.h>
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#include <asm/mach/time.h>
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#include "iomap.h"
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static int wdt_heartbeat = 30;
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#ifndef CONFIG_ARCH_TEGRA_2x_SOC
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#define TIMER_PTV 0
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#define TIMER_EN (1 << 31)
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#define TIMER_PERIODIC (1 << 30)
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#define TIMER_PCR 0x4
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#define TIMER_PCR_INTR (1 << 30)
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#define WDT_CFG (0)
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#define WDT_CFG_TMR_SRC (0 << 0) /* for TMR10. */
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#define WDT_CFG_PERIOD (1 << 4)
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#define WDT_CFG_INT_EN (1 << 12)
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#define WDT_CFG_SYS_RST_EN (1 << 14)
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#define WDT_CFG_PMC2CAR_RST_EN (1 << 15)
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#define WDT_CMD (8)
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#define WDT_CMD_START_COUNTER (1 << 0)
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#define WDT_CMD_DISABLE_COUNTER (1 << 1)
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#define WDT_UNLOCK (0xC)
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#define WDT_UNLOCK_PATTERN (0xC45A << 0)
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static void __iomem *wdt_timer = IO_ADDRESS(TEGRA_TMR10_BASE);
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static void __iomem *wdt_source = IO_ADDRESS(TEGRA_WDT3_BASE);
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static void tegra_wdt_reset_enable(void)
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{
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u32 val;
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writel(TIMER_PCR_INTR, wdt_timer + TIMER_PCR);
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val = (wdt_heartbeat * 1000000ul) / 4;
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val |= (TIMER_EN | TIMER_PERIODIC);
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writel(val, wdt_timer + TIMER_PTV);
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val = WDT_CFG_TMR_SRC | WDT_CFG_PERIOD | /*WDT_CFG_INT_EN |*/
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/*WDT_CFG_SYS_RST_EN |*/ WDT_CFG_PMC2CAR_RST_EN;
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writel(val, wdt_source + WDT_CFG);
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writel(WDT_CMD_START_COUNTER, wdt_source + WDT_CMD);
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pr_info("%s: WDT Recovery Enabled\n", __func__);
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}
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static int tegra_wdt_reset_disable(void)
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{
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writel(TIMER_PCR_INTR, wdt_timer + TIMER_PCR);
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writel(WDT_UNLOCK_PATTERN, wdt_source + WDT_UNLOCK);
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writel(WDT_CMD_DISABLE_COUNTER, wdt_source + WDT_CMD);
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writel(0, wdt_timer + TIMER_PTV);
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pr_info("%s: WDT Recovery Disabled\n", __func__);
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return 0;
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}
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#else
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static void tegra_wdt_reset_enable(void)
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{
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}
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static int tegra_wdt_reset_disable(void)
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{
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return 0;
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}
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#endif
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static int tegra_pm_notify(struct notifier_block *nb,
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unsigned long event, void *nouse)
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{
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switch (event) {
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case PM_SUSPEND_PREPARE:
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tegra_wdt_reset_enable();
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break;
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case PM_POST_SUSPEND:
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tegra_wdt_reset_disable();
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block tegra_wdt_notify = {
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.notifier_call = tegra_pm_notify,
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};
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static struct syscore_ops tegra_wdt_syscore_ops = {
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.suspend = tegra_wdt_reset_disable,
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.resume = tegra_wdt_reset_enable,
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};
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static int __init tegra_wdt_recovery_init(void)
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{
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#ifdef CONFIG_PM
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/* Register PM notifier. */
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register_pm_notifier(&tegra_wdt_notify);
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#endif
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register_syscore_ops(&tegra_wdt_syscore_ops);
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return 0;
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}
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subsys_initcall(tegra_wdt_recovery_init);
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