forked from rrcarlosr/Jetpack
136 lines
3.9 KiB
C
136 lines
3.9 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _LINUX_TEGRA19X_MCE_H
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#define _LINUX_TEGRA19X_MCE_H
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#ifdef CONFIG_ARCH_TEGRA_19x_SOC
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int tegra19x_mce_enter_cstate(u32 state, u32 wake_time);
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int tegra19x_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system,
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u8 force, u32 wake_mask, bool valid);
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int tegra19x_mce_update_crossover_time(u32 type, u32 time);
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int tegra19x_mce_read_cstate_stats(u32 state, u64 *stats);
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int tegra19x_mce_cc3_ctrl(u32 ndiv, u32 vindex, u8 enable);
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int tegra19x_mce_read_versions(u32 *major, u32 *minor);
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int tegra19x_mce_write_dda_ctrl(u32 index, u64 value);
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int tegra19x_mce_read_dda_ctrl(u32 index, u64 *value);
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#ifdef CONFIG_DEBUG_FS
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int tegra19x_mce_features_get(void *data, u64 *val);
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int tegra19x_mce_enable_latic_set(void *data, u64 val);
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int tegra19x_mce_coresight_cg_set(void *data, u64 val);
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int tegra19x_mce_edbgreq_set(void *data, u64 val);
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int tegra19x_mce_dbg_cstats_show(struct seq_file *s, void *data);
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int tegra19x_mce_read_rt_safe_mask(u64 *rt_safe_mask);
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int tegra19x_mce_write_rt_safe_mask(u64 rt_safe_mask);
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int tegra19x_mce_read_rt_window_us(u64 *rt_window_us);
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int tegra19x_mce_write_rt_window_us(u64 rt_window_us);
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int tegra19x_mce_read_rt_fwd_progress_us(u64 *rt_fwd_progress_us);
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int tegra19x_mce_write_rt_fwd_progress_us(u64 rt_fwd_progress_us);
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#endif
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/* Tegra19x cache functions */
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int t19x_flush_cache_all(void);
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int t19x_flush_dcache_all(void);
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int t19x_clean_dcache_all(void);
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/* Return L3 cache ways */
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int tegra19x_mce_read_l3_cache_ways(u64 *value);
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/* Write L3 cache ways and return L3 cache ways actually written */
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int tegra19x_mce_write_l3_cache_ways(u64 data, u64 *value);
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#else /* CONFIG_ARCH_TEGRA_19x_SOC */
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static int tegra19x_mce_enter_cstate(u32 state, u32 wake_time)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system,
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u8 force, u32 wake_mask, bool valid)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_update_crossover_time(u32 type, u32 time)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_read_cstate_stats(u32 state, u64 *stats)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_cc3_ctrl(u32 ndiv, u32 vindex, u8 enable)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_read_versions(u32 *major, u32 *minor)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_write_dda_ctrl(u32 index, u64 value)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_read_dda_ctrl(u32 index, u64 *value)
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{
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return -ENOTSUPP;
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}
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#ifdef CONFIG_DEBUG_FS
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static int tegra19x_mce_features_get(void *data, u64 *val)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_enable_latic_set(void *data, u64 val)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_coresight_cg_set(void *data, u64 val)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_edbgreq_set(void *data, u64 val)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_dbg_cstats_show(struct seq_file *s, void *data)
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{
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return -ENOTSUPP;
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}
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#endif /* CONFIG_DEBUG_FS */
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static int t19x_flush_cache_all(void)
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{
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return -ENOTSUPP;
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}
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static int t19x_flush_dcache_all(void)
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{
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return -ENOTSUPP;
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}
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static int t19x_clean_dcache_all(void)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_write_l3_cache_ways(u64 data, u64 *value)
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{
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return -ENOTSUPP;
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}
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static int tegra19x_mce_read_l3_cache_ways(u64 *value)
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{
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return -ENOTSUPP;
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}
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#endif /* CONFIG_ARCH_TEGRA_19x_SOC */
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#endif /* _LINUX_TEGRA19X_MCE_H */
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