forked from rrcarlosr/Jetpack
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <asm/traps.h>
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#include <linux/debugfs.h>
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#include <linux/debugfs.h>
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#include <linux/cpu_pm.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform/tegra/denver_mca.h>
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#include <linux/tegra-mce.h>
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#include <linux/t18x_ari.h>
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#include <soc/tegra/chip-id.h>
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/* Denver MCA */
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/* Instantiate all accessors for a bank */
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DEFINE_DENVER_MCA_OPS(0, 4, 0, 4, 1, 4, 2, 4, 3, 4, 4)
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DEFINE_DENVER_MCA_OPS(1, 4, 6, 4, 7, 5, 0, 5, 1, 5, 2)
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DEFINE_DENVER_MCA_OPS(2, 5, 4, 5, 5, 5, 6, 5, 7, 6, 0)
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DEFINE_DENVER_MCA_OPS(3, 6, 2, 6, 3, 6, 4, 6, 5, 6, 6)
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DEFINE_DENVER_MCA_OPS(4, 7, 0, 7, 1, 7, 2, 7, 3, 7, 4)
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DEFINE_DENVER_MCA_OPS(5, 7, 6, 7, 7, 8, 0, 8, 1, 8, 2)
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DEFINE_DENVER_MCA_OPS(6, 8, 4, 8, 5, 8, 6, 8, 7, 9, 0)
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DEFINE_DENVER_MCA_OPS(7, 9, 2, 9, 3, 9, 4, 9, 5, 9, 6)
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static struct denver_mca_error jsr_ret_errors[] = {
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{.name = "Internal timer error",
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.error_code = 0},
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{}
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};
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static struct denver_mca_error jsr_mts_errors[] = {
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{.name = "Internal unclasified error",
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.error_code = 4},
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{}
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};
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static struct denver_mca_bank denver_mca_banks[] = {
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{.name = "JSR:RET",
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DENVER_MCA_OP_ENTRY(0),
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.errors = jsr_ret_errors},
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{.name = "JSR:MTS",
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DENVER_MCA_OP_ENTRY(1),
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.errors = jsr_mts_errors},
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{SIMPLE_DENVER_MCA_OP_ENTRY("DCC:1", 2)},
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{SIMPLE_DENVER_MCA_OP_ENTRY("DCC:2", 3)},
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{SIMPLE_DENVER_MCA_OP_ENTRY("LVB:3", 4)},
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{SIMPLE_DENVER_MCA_OP_ENTRY("MM", 5)},
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{SIMPLE_DENVER_MCA_OP_ENTRY("L2", 6)},
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{SIMPLE_DENVER_MCA_OP_ENTRY("IFU", 7)},
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{}
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};
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static void tegra18_register_denver_mca_banks(void)
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{
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int i;
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for (i = 0; denver_mca_banks[i].name; i++)
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register_denver_mca_bank(&denver_mca_banks[i]);
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}
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static void tegra18_unregister_denver_mca_banks(void)
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{
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int i;
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for (i = 0; denver_mca_banks[i].name; i++)
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unregister_denver_mca_bank(&denver_mca_banks[i]);
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}
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/*
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* Without this enable set, Denver cores will halt on serrors
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* instead of continuing (if possible) to the kernel serror
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* handler
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*/
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static void tegra18_denver_serr_enable(void)
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{
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mca_cmd_t cmd;
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u32 error;
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u64 data;
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cmd.data = 0;
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cmd.cmd = TEGRA_ARI_MCA_WRITE_SERR;
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cmd.idx = TEGRA_ARI_MCA_RD_WR_GLOBAL_CONFIG_REGISTER;
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if (tegra_mce_write_uncore_mca(cmd, 1, &error))
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pr_err("%s:mce write failed: error=0x%x\n", __func__, error);
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cmd.cmd = TEGRA_ARI_MCA_READ_SERR;
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cmd.idx = TEGRA_ARI_MCA_RD_WR_CCE;
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cmd.subidx = TEGRA_ARI_MCA_RD_WR_ASERRX_MISC1;
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if (tegra_mce_read_uncore_mca(cmd, &data, &error))
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pr_err("%s:mce write failed: error=0x%x\n", __func__, error);
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cmd.cmd = TEGRA_ARI_MCA_WRITE_SERR;
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/* Disable Error Response (Data abort) on VPR reads.
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* set PSN_ERR_CORR_MASK[7] = 1.
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*/
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data |= 1 << 19;
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if (tegra_mce_write_uncore_mca(cmd, data, &error))
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pr_err("%s:mce write failed: error=0x%x\n", __func__, error);
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}
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static int __init tegra18_serr_init(void)
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{
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if (tegra_get_chip_id() != TEGRA186)
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return 0;
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tegra18_denver_serr_enable();
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tegra18_register_denver_mca_banks();
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return 0;
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}
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module_init(tegra18_serr_init);
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static void __exit tegra18_serr_exit(void)
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{
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tegra18_unregister_denver_mca_banks();
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}
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module_exit(tegra18_serr_exit);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Tegra T18x SError handler");
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