forked from rrcarlosr/Jetpack
854 lines
21 KiB
C
854 lines
21 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/debugfs.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/tegra-mce.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <soc/tegra/chip-id.h>
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#include "tegra18x-mce.h"
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#include "tegra19x-mce.h"
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#define SMC_SIP_INVOKE_MCE 0xC2FFFF00
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#define NR_SMC_REGS 6
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enum {
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TEGRA_MCE_ID_186,
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TEGRA_MCE_ID_194,
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TEGRA_MCE_ID_MAX,
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};
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static int tegra_mce_id = TEGRA_MCE_ID_MAX;
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static int (*_tegra_mce_enter_cstate)(u32, u32);
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static int (*_tegra_mce_update_cstate_info)(u32, u32, u32, u8, u32, bool);
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static int (*_tegra_mce_update_crossover_time)(u32, u32);
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static int (*_tegra_mce_read_cstate_stats)(u32, u64 *);
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static int (*_tegra_mce_write_cstate_stats)(u32, u32);
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static int (*_tegra_mce_is_sc7_allowed)(u32, u32, u32 *);
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static int (*_tegra_mce_online_core)(int);
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static int (*_tegra_mce_cc3_ctrl)(u32, u32, u8);
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static int (*_tegra_mce_echo_data)(u32, int *);
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static int (*_tegra_mce_read_versions)(u32 *, u32 *);
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static int (*_tegra_mce_enum_features)(u64 *);
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static int (*_tegra_mce_read_uncore_mca)(mca_cmd_t, u64 *, u32 *);
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static int (*_tegra_mce_write_uncore_mca)(mca_cmd_t, u64, u32 *);
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static int (*_tegra_mce_read_uncore_perfmon)(u32, u32 *);
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static int (*_tegra_mce_write_uncore_perfmon)(u32, u32);
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static int (*_tegra_mce_enable_latic)(void);
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static int (*_tegra_mce_write_dda_ctrl)(u32 index, u64 value);
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static int (*_tegra_mce_read_dda_ctrl)(u32 index, u64 *value);
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static int (*_tegra_mce_read_l3_cache_ways)(u64 *value);
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static int (*_tegra_mce_write_l3_cache_ways)(u64 data, u64 *value);
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static int (*_tegra_mce_read_rt_safe_mask)(u64 *);
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static int (*_tegra_mce_write_rt_safe_mask)(u64);
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static int (*_tegra_mce_read_rt_window_us)(u64 *);
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static int (*_tegra_mce_write_rt_window_us)(u64);
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static int (*_tegra_mce_read_rt_fwd_progress_us)(u64 *);
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static int (*_tegra_mce_write_rt_fwd_progress_us)(u64);
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/**
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* Specify power state and wake time for entering upon STANDBYWFI
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*
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* @state: requested core power state
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* @wake_time: wake time in TSC ticks
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*
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* Returns 0 if success.
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*/
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int tegra_mce_enter_cstate(u32 state, u32 wake_time)
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{
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if (!_tegra_mce_enter_cstate)
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return -ENOTSUPP;
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return _tegra_mce_enter_cstate(state, wake_time);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_enter_cstate);
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/**
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* Specify deepest cluster/ccplex/system states allowed.
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*
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* @cluster: deepest cluster-wide state
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* @ccplex: deepest ccplex-wide state
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* @system: deepest system-wide state
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* @force: forced system state
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* @wake_mask: wake mask to be updated
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* @valid: is wake_mask applicable?
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*
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* Returns 0 if success.
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*/
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int tegra_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system,
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u8 force, u32 wake_mask, bool valid)
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{
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if (!_tegra_mce_update_cstate_info)
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return -ENOTSUPP;
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return _tegra_mce_update_cstate_info(cluster, ccplex, system,
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force, wake_mask, valid);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_update_cstate_info);
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/**
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* Update threshold for one specific c-state crossover
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*
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* @type: type of state crossover.
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* @time: idle time threshold.
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*
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* Returns 0 if success.
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*/
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int tegra_mce_update_crossover_time(u32 type, u32 time)
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{
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if (!_tegra_mce_update_crossover_time)
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return -ENOTSUPP;
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return _tegra_mce_update_crossover_time(type, time);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_update_crossover_time);
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/**
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* Query the runtime stats of a specific cstate
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*
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* @state: c-state of the stats.
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* @stats: output integer to hold the stats.
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*
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* Returns 0 if success.
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*/
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int tegra_mce_read_cstate_stats(u32 state, u64 *stats)
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{
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if (!_tegra_mce_read_cstate_stats)
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return -ENOTSUPP;
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return _tegra_mce_read_cstate_stats(state, stats);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_cstate_stats);
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/**
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* Overwrite the runtime stats of a specific c-state
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*
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* @state: c-state of the stats.
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* @stats: integer represents the new stats.
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*
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* Returns 0 if success.
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*/
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int tegra_mce_write_cstate_stats(u32 state, u32 stats)
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{
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if (!_tegra_mce_write_cstate_stats)
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return -ENOTSUPP;
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return _tegra_mce_write_cstate_stats(state, stats);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_cstate_stats);
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/**
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* Query MCE to determine if SC7 is allowed
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* given a target core's C-state and wake time
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*
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* @state: c-state of the stats.
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* @stats: integer represents the new stats.
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* @allowed: pointer to result
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*
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* Returns 0 if success.
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*/
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int tegra_mce_is_sc7_allowed(u32 state, u32 wake, u32 *allowed)
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{
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if (!_tegra_mce_is_sc7_allowed)
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return -ENOTSUPP;
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return _tegra_mce_is_sc7_allowed(state, wake, allowed);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_is_sc7_allowed);
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/**
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* Bring another offlined core back online to C0 state.
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*
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* @cpu: logical cpuid from smp_processor_id()
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*
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* Returns 0 if success.
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*/
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int tegra_mce_online_core(int cpu)
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{
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if (!_tegra_mce_online_core)
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return -ENOTSUPP;
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return _tegra_mce_online_core(cpu);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_online_core);
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/**
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* Program Auto-CC3 feature.
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*
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* @ndiv: ndiv of IDLE voltage/freq register
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* @vindex: vindex of IDLE voltage/freq register
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* (Not used on tegra19x)
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* @enable: enable bit for Auto-CC3
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*
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* Returns 0 if success.
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*/
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int tegra_mce_cc3_ctrl(u32 ndiv, u32 vindex, u8 enable)
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{
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if (!_tegra_mce_cc3_ctrl)
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return -ENOTSUPP;
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return _tegra_mce_cc3_ctrl(ndiv, vindex, enable);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_cc3_ctrl);
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/**
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* Send data to MCE which echoes it back.
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*
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* @data: data to be sent to MCE.
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* @out: output data to hold the response.
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* @matched: pointer to matching result
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*
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* Returns 0 if success.
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*/
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int tegra_mce_echo_data(u32 data, int *matched)
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{
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if (!_tegra_mce_echo_data)
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return -ENOTSUPP;
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return _tegra_mce_echo_data(data, matched);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_echo_data);
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/**
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* Read out MCE API major/minor versions
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*
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* @major: output for major number.
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* @minor: output for minor number.
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*
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* Returns 0 if success.
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*/
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int tegra_mce_read_versions(u32 *major, u32 *minor)
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{
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if (!_tegra_mce_read_versions)
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return -ENOTSUPP;
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return _tegra_mce_read_versions(major, minor);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_versions);
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/**
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* Read out RT Safe Mask
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*
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* @rt_safe_mask: output for rt safe mask.
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*
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* Returns 0 if success.
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*/
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int tegra_mce_read_rt_safe_mask(u64 *rt_safe_mask)
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{
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if (!_tegra_mce_read_rt_safe_mask)
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return -ENOTSUPP;
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return _tegra_mce_read_rt_safe_mask(rt_safe_mask);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_rt_safe_mask);
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/**
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* Write RT Safe Mask
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*
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* @rt_safe_mask: rt safe mask value to be written
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*
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* Returns 0 if success.
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*/
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int tegra_mce_write_rt_safe_mask(u64 rt_safe_mask)
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{
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if (!_tegra_mce_write_rt_safe_mask)
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return -ENOTSUPP;
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return _tegra_mce_write_rt_safe_mask(rt_safe_mask);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_rt_safe_mask);
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/**
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* Read out RT Window US
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*
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* @rt_window_us: output for rt window us
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*
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* Returns 0 if success.
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*/
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int tegra_mce_read_rt_window_us(u64 *rt_window_us)
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{
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if (!_tegra_mce_read_rt_window_us)
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return -ENOTSUPP;
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return _tegra_mce_read_rt_window_us(rt_window_us);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_rt_window_us);
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/**
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* Write RT Window US
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*
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* @rt_window_us: rt window us value to be written
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*
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* Returns 0 if success.
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*/
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int tegra_mce_write_rt_window_us(u64 rt_window_us)
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{
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if (!_tegra_mce_write_rt_window_us)
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return -ENOTSUPP;
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return _tegra_mce_write_rt_window_us(rt_window_us);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_rt_window_us);
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/**
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* Read out RT Fwd Progress US
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*
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* @rt_fwd_progress_us: output for rt fwd progress us
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*
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* Returns 0 if success.
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*/
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int tegra_mce_read_rt_fwd_progress_us(u64 *rt_fwd_progress_us)
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{
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if (!_tegra_mce_read_rt_fwd_progress_us)
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return -ENOTSUPP;
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return _tegra_mce_read_rt_fwd_progress_us(rt_fwd_progress_us);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_rt_fwd_progress_us);
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/**
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* Write RT Fwd Progress US
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*
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* @rt_fwd_progress_us: rt fwd progress us value to be written
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*
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* Returns 0 if success.
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*/
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int tegra_mce_write_rt_fwd_progress_us(u64 rt_fwd_progress_us)
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{
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if (!_tegra_mce_write_rt_fwd_progress_us)
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return -ENOTSUPP;
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return _tegra_mce_write_rt_fwd_progress_us(rt_fwd_progress_us);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_rt_fwd_progress_us);
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/**
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* Enumerate MCE API features
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*
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* @features: output feature vector (4bits each)
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*
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* Returns 0 if success.
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*/
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int tegra_mce_enum_features(u64 *features)
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{
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if (!_tegra_mce_enum_features)
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return -ENOTSUPP;
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return _tegra_mce_enum_features(features);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_enum_features);
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/**
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* Read uncore MCA errors.
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*
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* @cmd: MCA command
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* @data: output data for the command
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* @error: error from MCA
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*
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* Returns 0 if success.
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*/
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int tegra_mce_read_uncore_mca(mca_cmd_t cmd, u64 *data, u32 *error)
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{
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if (!_tegra_mce_read_uncore_mca)
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return -ENOTSUPP;
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return _tegra_mce_read_uncore_mca(cmd, data, error);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_uncore_mca);
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/**
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* Write uncore MCA errors.
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*
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* @cmd: MCA command
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* @data: input data for the command
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* @error: error from MCA
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*
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* Returns 0 if success.
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*/
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int tegra_mce_write_uncore_mca(mca_cmd_t cmd, u64 data, u32 *error)
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{
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if (!_tegra_mce_write_uncore_mca)
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return -ENOTSUPP;
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return _tegra_mce_write_uncore_mca(cmd, data, error);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_uncore_mca);
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/**
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* Query PMU for uncore perfmon counter
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*
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* @req input command and counter index
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* @data output counter value
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*
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* Returns status of read request.
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*/
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int tegra_mce_read_uncore_perfmon(u32 req, u32 *data)
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{
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if (!_tegra_mce_read_uncore_perfmon)
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return -ENOTSUPP;
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return _tegra_mce_read_uncore_perfmon(req, data);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_uncore_perfmon);
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/**
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* Write PMU reg for uncore perfmon counter
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*
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* @req input command and counter index
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* @data data to be written
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*
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* Returns status of write request.
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*/
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int tegra_mce_write_uncore_perfmon(u32 req, u32 data)
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{
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if (!_tegra_mce_write_uncore_perfmon)
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return -ENOTSUPP;
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return _tegra_mce_write_uncore_perfmon(req, data);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_uncore_perfmon);
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int tegra_mce_enable_latic(void)
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{
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if (!_tegra_mce_enable_latic)
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return -ENOTSUPP;
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return _tegra_mce_enable_latic();
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}
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EXPORT_SYMBOL_GPL(tegra_mce_enable_latic);
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/**
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* Write to NVG DDA registers
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*
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* @index: NVG communication channel id
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* @value: Register value to be written
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*
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* Returns 0 on success
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*/
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int tegra_mce_write_dda_ctrl(u32 index, u64 value)
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{
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if(!_tegra_mce_write_dda_ctrl)
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return -ENOTSUPP;
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return _tegra_mce_write_dda_ctrl(index, value);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_dda_ctrl);
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/**
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* Read NVG DDA registers
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*
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* @index: NVG communication channel id
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* @value: Associated register value read
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*
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* Returns 0 on success
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*/
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int tegra_mce_read_dda_ctrl(u32 index, u64 *value)
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{
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if(!_tegra_mce_read_dda_ctrl)
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return -ENOTSUPP;
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return _tegra_mce_read_dda_ctrl(index, value);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_dda_ctrl);
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/**
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* Read NVG L3 cache control register
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*
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* @value: Fill L3 cache ways
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*
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* Returns 0 on success
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*/
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int tegra_mce_read_l3_cache_ways(u64 *value)
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{
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if (!_tegra_mce_read_l3_cache_ways)
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return -ENOTSUPP;
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return _tegra_mce_read_l3_cache_ways(value);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_read_l3_cache_ways);
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/**
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* Write L3 cache ways and read back the l3 cache ways written
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*
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* @data: L3 cache ways to be writtein
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* @value: L3 cache ways returrned back
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*
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* Returns 0 on success
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*/
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int tegra_mce_write_l3_cache_ways(u64 data, u64 *value)
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{
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if (!_tegra_mce_write_l3_cache_ways)
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return -ENOTSUPP;
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return _tegra_mce_write_l3_cache_ways(data, value);
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}
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EXPORT_SYMBOL_GPL(tegra_mce_write_l3_cache_ways);
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *mce_debugfs;
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static int tegra_mce_echo_set(void *data, u64 val)
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{
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u32 matched;
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int ret;
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ret = tegra_mce_echo_data((u32)val, &matched);
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if (ret && ret != -ENOTSUPP)
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return -EINVAL;
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return 0;
|
|
}
|
|
|
|
static int tegra_mce_versions_get(void *data, u64 *val)
|
|
{
|
|
u32 major, minor;
|
|
int ret;
|
|
|
|
ret = tegra_mce_read_versions(&major, &minor);
|
|
if (!ret)
|
|
*val = ((u64)major << 32) | minor;
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_mce_rt_safe_mask_get(void *data, u64 *val)
|
|
{
|
|
u64 rt_safe_mask;
|
|
int ret;
|
|
|
|
ret = tegra_mce_read_rt_safe_mask(&rt_safe_mask);
|
|
if (!ret)
|
|
*val = rt_safe_mask;
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_mce_rt_safe_mask_set(void *data, u64 val)
|
|
{
|
|
int ret;
|
|
|
|
ret = tegra_mce_write_rt_safe_mask(val);
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_mce_rt_window_us_get(void *data, u64 *val)
|
|
{
|
|
u64 rt_window_us;
|
|
int ret;
|
|
|
|
ret = tegra_mce_read_rt_window_us(&rt_window_us);
|
|
if (!ret)
|
|
*val = rt_window_us;
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_mce_rt_window_us_set(void *data, u64 val)
|
|
{
|
|
int ret;
|
|
|
|
ret = tegra_mce_write_rt_window_us(val);
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_mce_rt_fwd_progress_us_get(void *data, u64 *val)
|
|
{
|
|
u64 rt_fwd_progress_us;
|
|
int ret;
|
|
|
|
ret = tegra_mce_read_rt_fwd_progress_us(&rt_fwd_progress_us);
|
|
if (!ret)
|
|
*val = rt_fwd_progress_us;
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_mce_rt_fwd_progress_us_set(void *data, u64 val)
|
|
{
|
|
int ret;
|
|
|
|
ret = tegra_mce_write_rt_fwd_progress_us(val);
|
|
return ret;
|
|
}
|
|
|
|
#define TEGRA_MCE_DBGFS_FUNC(name, type1, param1, type2, param2) \
|
|
static int tegra_##name(type1 param1, type2 param2) \
|
|
{ \
|
|
int (*f)(type1, type2) = NULL; \
|
|
\
|
|
switch (tegra_mce_id) { \
|
|
case TEGRA_MCE_ID_186: \
|
|
f = tegra18x_##name; \
|
|
break; \
|
|
case TEGRA_MCE_ID_194: \
|
|
f = tegra19x_##name; \
|
|
break; \
|
|
default: \
|
|
return -ENOTSUPP; \
|
|
} \
|
|
return f ? f(param1, param2) : -ENOTSUPP; \
|
|
}
|
|
|
|
TEGRA_MCE_DBGFS_FUNC(mce_features_get, void *, data, u64 *, val);
|
|
TEGRA_MCE_DBGFS_FUNC(mce_enable_latic_set, void *, data, u64, val);
|
|
TEGRA_MCE_DBGFS_FUNC(mce_coresight_cg_set, void *, data, u64, val);
|
|
TEGRA_MCE_DBGFS_FUNC(mce_edbgreq_set, void *, data, u64, val);
|
|
|
|
static int tegra_mce_dbg_cstats_open(struct inode *inode, struct file *file)
|
|
{
|
|
int (*f)(struct seq_file *, void *);
|
|
|
|
switch (tegra_mce_id) {
|
|
case TEGRA_MCE_ID_186:
|
|
f = tegra18x_mce_dbg_cstats_show;
|
|
break;
|
|
case TEGRA_MCE_ID_194:
|
|
f = tegra19x_mce_dbg_cstats_show;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return single_open(file, f, inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations tegra_mce_cstats_fops = {
|
|
.open = tegra_mce_dbg_cstats_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_echo_fops, NULL,
|
|
tegra_mce_echo_set, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_versions_fops, tegra_mce_versions_get,
|
|
NULL, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_features_fops, tegra_mce_features_get,
|
|
NULL, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_enable_latic_fops, NULL,
|
|
tegra_mce_enable_latic_set, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_coresight_cg_fops, NULL,
|
|
tegra_mce_coresight_cg_set, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_edbgreq_fops, NULL,
|
|
tegra_mce_edbgreq_set, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_rt_safe_mask_fops, tegra_mce_rt_safe_mask_get,
|
|
tegra_mce_rt_safe_mask_set, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_rt_window_us_fops, tegra_mce_rt_window_us_get,
|
|
tegra_mce_rt_window_us_set, "%llu\n");
|
|
DEFINE_SIMPLE_ATTRIBUTE(tegra_mce_rt_fwd_progress_us_fops,
|
|
tegra_mce_rt_fwd_progress_us_get,
|
|
tegra_mce_rt_fwd_progress_us_set, "%llu\n");
|
|
|
|
struct debugfs_entry {
|
|
const char *name;
|
|
const struct file_operations *fops;
|
|
mode_t mode;
|
|
};
|
|
|
|
/* Make sure to put an NULL entry at the end of each group */
|
|
static struct debugfs_entry tegra18x_mce_attrs[] = {
|
|
{ "echo", &tegra_mce_echo_fops, 0200 },
|
|
{ "versions", &tegra_mce_versions_fops, 0444 },
|
|
{ "features", &tegra_mce_features_fops, 0444 },
|
|
{ "cstats", &tegra_mce_cstats_fops, 0444 },
|
|
{ "enable-latic", &tegra_mce_enable_latic_fops, 0200 },
|
|
{ "coresight_cg_enable", &tegra_mce_coresight_cg_fops, 0200 },
|
|
{ "edbgreq", &tegra_mce_edbgreq_fops, 0200 },
|
|
{ NULL, NULL, 0 },
|
|
};
|
|
|
|
static struct debugfs_entry tegra19x_mce_attrs[] = {
|
|
{ "versions", &tegra_mce_versions_fops, 0444 },
|
|
{ "cstats", &tegra_mce_cstats_fops, 0444 },
|
|
{ "rt_safe_mask", &tegra_mce_rt_safe_mask_fops, 0644 },
|
|
{ "rt_window_us", &tegra_mce_rt_window_us_fops, 0644 },
|
|
{ "rt_fwd_progress_us", &tegra_mce_rt_fwd_progress_us_fops, 0644 },
|
|
{ NULL, NULL, 0 }
|
|
};
|
|
|
|
static struct debugfs_entry *tegra_mce_attrs[TEGRA_MCE_ID_MAX] = {
|
|
tegra18x_mce_attrs,
|
|
tegra19x_mce_attrs,
|
|
};
|
|
|
|
static __init int tegra_mce_init(void)
|
|
{
|
|
struct debugfs_entry *fent;
|
|
struct dentry *dent;
|
|
int ret;
|
|
|
|
if (tegra_mce_id >= TEGRA_MCE_ID_MAX)
|
|
return -ENOTSUPP;
|
|
|
|
mce_debugfs = debugfs_create_dir("tegra_mce", NULL);
|
|
if (!mce_debugfs)
|
|
return -ENOMEM;
|
|
|
|
for (fent = tegra_mce_attrs[tegra_mce_id]; fent->name; fent++) {
|
|
dent = debugfs_create_file(fent->name, fent->mode,
|
|
mce_debugfs, NULL, fent->fops);
|
|
if (IS_ERR_OR_NULL(dent)) {
|
|
ret = dent ? PTR_ERR(dent) : -EINVAL;
|
|
pr_err("%s: failed to create debugfs (%s): %d\n",
|
|
__func__, fent->name, ret);
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
pr_debug("%s: init finished\n", __func__);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
debugfs_remove_recursive(mce_debugfs);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit tegra_mce_exit(void)
|
|
{
|
|
if (tegra_mce_id >= TEGRA_MCE_ID_MAX)
|
|
return;
|
|
|
|
debugfs_remove_recursive(mce_debugfs);
|
|
}
|
|
module_init(tegra_mce_init);
|
|
module_exit(tegra_mce_exit);
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
|
|
/*
|
|
* Tegra cache functions
|
|
*
|
|
* Return 0 if success or -ENOTSUPP.
|
|
*
|
|
*/
|
|
int tegra_flush_cache_all(void)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (tegra_get_chip_id()) {
|
|
case TEGRA186:
|
|
ret = tegra18x_roc_flush_cache();
|
|
break;
|
|
case TEGRA194:
|
|
ret = t19x_flush_cache_all();
|
|
/* Fallback to VA flush cache all if not support or failed */
|
|
if (ret)
|
|
flush_cache_all();
|
|
break;
|
|
default:
|
|
flush_cache_all();
|
|
break;
|
|
}
|
|
|
|
/* CRITICAL: failed to flush all cache */
|
|
WARN_ON(ret && ret != -ENOTSUPP);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(tegra_flush_cache_all);
|
|
|
|
int tegra_flush_dcache_all(void *__maybe_unused unused)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (tegra_get_chip_id()) {
|
|
case TEGRA186:
|
|
ret = tegra18x_roc_flush_cache_only();
|
|
break;
|
|
case TEGRA194:
|
|
ret = t19x_flush_dcache_all();
|
|
/* Fallback to VA flush dcache if not support or failed */
|
|
if (ret)
|
|
__flush_dcache_all(unused);
|
|
break;
|
|
default:
|
|
__flush_dcache_all(unused);
|
|
break;
|
|
}
|
|
|
|
/* CRITICAL: failed to flush dcache */
|
|
WARN_ON(ret && ret != -ENOTSUPP);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(tegra_flush_dcache_all);
|
|
|
|
int tegra_clean_dcache_all(void *__maybe_unused unused)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (tegra_get_chip_id()) {
|
|
case TEGRA186:
|
|
ret = tegra18x_roc_clean_cache();
|
|
break;
|
|
case TEGRA194:
|
|
ret = t19x_clean_dcache_all();
|
|
/* Fallback to VA clean if not support or failed */
|
|
if (ret)
|
|
__clean_dcache_all(unused);
|
|
break;
|
|
default:
|
|
__clean_dcache_all(unused);
|
|
break;
|
|
}
|
|
|
|
/* CRITICAL: failed to clean dcache */
|
|
WARN_ON(ret && ret != -ENOTSUPP);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(tegra_clean_dcache_all);
|
|
|
|
/* Make sure functions will be available for other drivers */
|
|
static __init int tegra_mce_early_init(void)
|
|
{
|
|
switch (tegra_get_chip_id()) {
|
|
case TEGRA186:
|
|
tegra_mce_id = TEGRA_MCE_ID_186;
|
|
_tegra_mce_enter_cstate = tegra18x_mce_enter_cstate;
|
|
_tegra_mce_update_cstate_info = tegra18x_mce_update_cstate_info;
|
|
_tegra_mce_update_crossover_time =
|
|
tegra18x_mce_update_crossover_time;
|
|
_tegra_mce_read_cstate_stats = tegra18x_mce_read_cstate_stats;
|
|
_tegra_mce_write_cstate_stats = tegra18x_mce_write_cstate_stats;
|
|
_tegra_mce_is_sc7_allowed = tegra18x_mce_is_sc7_allowed;
|
|
_tegra_mce_online_core = tegra18x_mce_online_core;
|
|
_tegra_mce_cc3_ctrl = tegra18x_mce_cc3_ctrl;
|
|
_tegra_mce_echo_data = tegra18x_mce_echo_data;
|
|
_tegra_mce_read_versions = tegra18x_mce_read_versions;
|
|
_tegra_mce_enum_features = tegra18x_mce_enum_features;
|
|
_tegra_mce_read_uncore_mca = tegra18x_mce_read_uncore_mca;
|
|
_tegra_mce_write_uncore_mca = tegra18x_mce_write_uncore_mca;
|
|
_tegra_mce_read_uncore_perfmon =
|
|
tegra18x_mce_read_uncore_perfmon;
|
|
_tegra_mce_write_uncore_perfmon =
|
|
tegra18x_mce_write_uncore_perfmon;
|
|
_tegra_mce_enable_latic = tegra18x_mce_enable_latic;
|
|
break;
|
|
case TEGRA194:
|
|
tegra_mce_id = TEGRA_MCE_ID_194;
|
|
_tegra_mce_enter_cstate = tegra19x_mce_enter_cstate;
|
|
_tegra_mce_update_cstate_info = tegra19x_mce_update_cstate_info;
|
|
_tegra_mce_update_crossover_time =
|
|
tegra19x_mce_update_crossover_time;
|
|
_tegra_mce_read_cstate_stats = tegra19x_mce_read_cstate_stats;
|
|
_tegra_mce_cc3_ctrl = tegra19x_mce_cc3_ctrl;
|
|
_tegra_mce_read_versions = tegra19x_mce_read_versions;
|
|
_tegra_mce_write_dda_ctrl = tegra19x_mce_write_dda_ctrl;
|
|
_tegra_mce_read_dda_ctrl = tegra19x_mce_read_dda_ctrl;
|
|
_tegra_mce_read_l3_cache_ways = tegra19x_mce_read_l3_cache_ways;
|
|
_tegra_mce_write_l3_cache_ways =
|
|
tegra19x_mce_write_l3_cache_ways;
|
|
#ifdef CONFIG_DEBUG_FS
|
|
_tegra_mce_read_rt_safe_mask = tegra19x_mce_read_rt_safe_mask;
|
|
_tegra_mce_write_rt_safe_mask = tegra19x_mce_write_rt_safe_mask;
|
|
_tegra_mce_read_rt_window_us = tegra19x_mce_read_rt_window_us;
|
|
_tegra_mce_write_rt_window_us = tegra19x_mce_write_rt_window_us;
|
|
_tegra_mce_read_rt_fwd_progress_us =
|
|
tegra19x_mce_read_rt_fwd_progress_us;
|
|
_tegra_mce_write_rt_fwd_progress_us =
|
|
tegra19x_mce_write_rt_fwd_progress_us;
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
break;
|
|
default:
|
|
/* Do not support any other platform */
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(tegra_mce_early_init);
|
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra MCE driver");
|
|
MODULE_AUTHOR("NVIDIA Corporation");
|
|
MODULE_LICENSE("GPL v2");
|