forked from rrcarlosr/Jetpack
307 lines
7.6 KiB
C
307 lines
7.6 KiB
C
/*
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* dev-t21x.c
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*
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* A device driver for ADSP and APE
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*
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* Copyright (C) 2014-2017, NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/tegra_nvadsp.h>
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#include <linux/clk/tegra.h>
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#include <linux/delay.h>
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#include <linux/reset.h>
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#include "dev.h"
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#include "amc.h"
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#include "dev-t21x.h"
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#ifdef CONFIG_PM
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static void nvadsp_clocks_disable(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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if (drv_data->adsp_clk) {
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clk_disable_unprepare(drv_data->adsp_clk);
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dev_dbg(dev, "adsp clocks disabled\n");
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drv_data->adsp_clk = NULL;
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}
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if (drv_data->adsp_cpu_abus_clk) {
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clk_disable_unprepare(drv_data->adsp_cpu_abus_clk);
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dev_dbg(dev, "adsp cpu abus clock disabled\n");
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drv_data->adsp_cpu_abus_clk = NULL;
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}
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if (drv_data->adsp_neon_clk) {
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clk_disable_unprepare(drv_data->adsp_neon_clk);
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dev_dbg(dev, "adsp_neon clocks disabled\n");
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drv_data->adsp_neon_clk = NULL;
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}
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if (drv_data->ape_clk) {
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clk_disable_unprepare(drv_data->ape_clk);
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dev_dbg(dev, "ape clock disabled\n");
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drv_data->ape_clk = NULL;
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}
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if (drv_data->apb2ape_clk) {
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clk_disable_unprepare(drv_data->apb2ape_clk);
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dev_dbg(dev, "apb2ape clock disabled\n");
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drv_data->apb2ape_clk = NULL;
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}
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}
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static int nvadsp_clocks_enable(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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int ret = 0;
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drv_data->ape_clk = devm_clk_get(dev, "adsp.ape");
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if (IS_ERR_OR_NULL(drv_data->ape_clk)) {
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dev_err(dev, "unable to find adsp.ape clock\n");
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ret = PTR_ERR(drv_data->ape_clk);
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goto end;
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}
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ret = clk_prepare_enable(drv_data->ape_clk);
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if (ret) {
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dev_err(dev, "unable to enable adsp.ape clock\n");
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goto end;
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}
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dev_dbg(dev, "ape clock enabled\n");
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drv_data->adsp_clk = devm_clk_get(dev, "adsp");
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if (IS_ERR_OR_NULL(drv_data->adsp_clk)) {
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dev_err(dev, "unable to find adsp clock\n");
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ret = PTR_ERR(drv_data->adsp_clk);
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goto end;
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}
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ret = clk_prepare_enable(drv_data->adsp_clk);
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if (ret) {
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dev_err(dev, "unable to enable adsp clock\n");
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goto end;
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}
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drv_data->adsp_cpu_abus_clk = devm_clk_get(dev, "adsp_cpu_abus");
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if (IS_ERR_OR_NULL(drv_data->adsp_cpu_abus_clk)) {
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dev_err(dev, "unable to find adsp cpu abus clock\n");
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ret = PTR_ERR(drv_data->adsp_cpu_abus_clk);
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goto end;
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}
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ret = clk_prepare_enable(drv_data->adsp_cpu_abus_clk);
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if (ret) {
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dev_err(dev, "unable to enable adsp cpu abus clock\n");
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goto end;
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}
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drv_data->adsp_neon_clk = devm_clk_get(dev, "adspneon");
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if (IS_ERR_OR_NULL(drv_data->adsp_neon_clk)) {
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dev_err(dev, "unable to find adsp neon clock\n");
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ret = PTR_ERR(drv_data->adsp_neon_clk);
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goto end;
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}
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ret = clk_prepare_enable(drv_data->adsp_neon_clk);
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if (ret) {
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dev_err(dev, "unable to enable adsp neon clock\n");
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goto end;
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}
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dev_dbg(dev, "adsp cpu clock enabled\n");
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drv_data->apb2ape_clk = devm_clk_get(dev, "adsp.apb2ape");
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if (IS_ERR_OR_NULL(drv_data->apb2ape_clk)) {
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dev_err(dev, "unable to find adsp.apb2ape clk\n");
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ret = PTR_ERR(drv_data->apb2ape_clk);
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goto end;
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}
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ret = clk_prepare_enable(drv_data->apb2ape_clk);
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if (ret) {
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dev_err(dev, "unable to enable adsp.apb2ape clock\n");
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goto end;
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}
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/* AHUB clock, UART clock is not being enabled as UART by default is
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* disabled on t210
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*/
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dev_dbg(dev, "all clocks enabled\n");
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return 0;
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end:
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nvadsp_clocks_disable(pdev);
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return ret;
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}
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static inline bool nvadsp_amsic_skip_reg(u32 offset)
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{
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if (offset == AMISC_ADSP_L2_REGFILEBASE ||
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offset == AMISC_SHRD_SMP_STA ||
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(offset >= AMISC_SEM_REG_START && offset <= AMISC_SEM_REG_END) ||
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offset == AMISC_TSC ||
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offset == AMISC_ACTMON_AVG_CNT) {
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return true;
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} else {
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return false;
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}
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}
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static int nvadsp_amisc_save(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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u32 val, offset;
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int i = 0;
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offset = AMISC_REG_START_OFFSET;
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while (offset <= AMISC_REG_MBOX_OFFSET) {
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if (nvadsp_amsic_skip_reg(offset)) {
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offset += 4;
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continue;
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}
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val = readl(d->base_regs[AMISC] + offset);
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d->state.amisc_regs[i++] = val;
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offset += 4;
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}
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offset = ADSP_ACTMON_REG_START_OFFSET;
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while (offset <= ADSP_ACTMON_REG_END_OFFSET) {
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if (nvadsp_amsic_skip_reg(offset)) {
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offset += 4;
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continue;
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}
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val = readl(d->base_regs[AMISC] + offset);
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d->state.amisc_regs[i++] = val;
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offset += 4;
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}
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return 0;
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}
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static int nvadsp_amisc_restore(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *d = platform_get_drvdata(pdev);
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u32 val, offset;
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int i = 0;
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offset = AMISC_REG_START_OFFSET;
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while (offset <= AMISC_REG_MBOX_OFFSET) {
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if (nvadsp_amsic_skip_reg(offset)) {
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offset += 4;
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continue;
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}
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val = d->state.amisc_regs[i++];
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writel(val, d->base_regs[AMISC] + offset);
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offset += 4;
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}
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offset = ADSP_ACTMON_REG_START_OFFSET;
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while (offset <= ADSP_ACTMON_REG_END_OFFSET) {
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if (nvadsp_amsic_skip_reg(offset)) {
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offset += 4;
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continue;
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}
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val = d->state.amisc_regs[i++];
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writel(val, d->base_regs[AMISC] + offset);
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offset += 4;
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}
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return 0;
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}
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static int __nvadsp_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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int ret = 0;
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dev_dbg(dev, "restoring adsp base regs\n");
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drv_data->base_regs = drv_data->base_regs_saved;
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dev_dbg(dev, "enabling clocks\n");
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ret = nvadsp_clocks_enable(pdev);
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if (ret) {
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dev_err(dev, "nvadsp_clocks_enable failed\n");
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goto skip;
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}
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if (!drv_data->adsp_os_suspended) {
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dev_dbg(dev, "%s: adsp os is not suspended\n", __func__);
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goto skip;
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}
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dev_dbg(dev, "restoring ape state\n");
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nvadsp_amc_restore(pdev);
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nvadsp_aram_restore(pdev);
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nvadsp_amisc_restore(pdev);
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skip:
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return ret;
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}
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static int __nvadsp_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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int ret = 0;
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if (!drv_data->adsp_os_suspended) {
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dev_dbg(dev, "%s: adsp os is not suspended\n", __func__);
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goto clocks;
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}
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dev_dbg(dev, "saving amsic\n");
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nvadsp_amisc_save(pdev);
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dev_dbg(dev, "saving aram\n");
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nvadsp_aram_save(pdev);
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dev_dbg(dev, "saving amc\n");
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nvadsp_amc_save(pdev);
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clocks:
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dev_dbg(dev, "disabling clocks\n");
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nvadsp_clocks_disable(pdev);
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dev_dbg(dev, "locking out adsp base regs\n");
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drv_data->base_regs = NULL;
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return ret;
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}
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static int __nvadsp_runtime_idle(struct device *dev)
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{
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return 0;
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}
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int nvadsp_pm_t21x_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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drv_data->runtime_suspend = __nvadsp_runtime_suspend;
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drv_data->runtime_resume = __nvadsp_runtime_resume;
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drv_data->runtime_idle = __nvadsp_runtime_idle;
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return 0;
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}
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#endif /* CONFIG_PM */
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int nvadsp_reset_t21x_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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int ret = 0;
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drv_data->adspall_rst = devm_reset_control_get(dev, "adspall");
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if (IS_ERR_OR_NULL(drv_data->adspall_rst)) {
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ret = PTR_ERR(drv_data->adspall_rst);
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dev_err(dev, "unable to get adspall reset %d\n", ret);
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}
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return ret;
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}
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