forked from rrcarlosr/Jetpack
331 lines
7.7 KiB
C
331 lines
7.7 KiB
C
/*
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* Copyright (C) 2015-2016, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/platform_device.h>
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#include <linux/platform/tegra/clock.h>
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#include <linux/irqchip/tegra-agic.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include "dev.h"
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#define ACTMON_DEV_CTRL 0x00
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#define ACTMON_DEV_CTRL_ENB (0x1 << 31)
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#define ACTMON_DEV_CTRL_AT_END_ENB (0x1 << 15)
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#define ACTMON_DEV_CTRL_PERIODIC_ENB (0x1 << 13)
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#define ACTMON_DEV_CTRL_SAMPLE_PERIOD_VAL_SHIFT (0)
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#define ACTMON_DEV_CTRL_SAMPLE_PERIOD_MASK (0xff << 0)
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#define ACTMON_DEV_COUNT 0x18
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#define ACTMON_DEV_INTR_STATUS 0x20
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#define ACTMON_DEV_INTR_AT_END (0x1 << 27)
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#define ACTMON_DEV_COUNT_WEGHT 0x24
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#define ACTMON_DEV_SAMPLE_CTRL 0x28
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#define ACTMON_DEV_SAMPLE_CTRL_TICK_65536 (0x1 << 2)
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#define ACTMON_DEV_SAMPLE_CTRL_TICK_256 (0x0 << 1)
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#define AMISC_ACTMON_0 0x54
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#define AMISC_ACTMON_CNT_TARGET_ENABLE (0x1 << 31)
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#define ACTMON_REG_OFFSET 0x800
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/* milli second divider as SAMPLE_TICK*/
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#define SAMPLE_MS_DIVIDER 65536
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struct adsp_cpustat {
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int irq;
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struct device *device;
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const char *dev_id;
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spinlock_t lock;
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struct clk *ape_clk;
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struct clk *adsp_clk;
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unsigned long ape_freq;
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unsigned long adsp_freq;
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u64 cur_usage;
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bool enable;
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u64 max_usage;
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void __iomem *base;
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};
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static struct adsp_cpustat cpustat;
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static struct adsp_cpustat *cpumon;
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static inline u32 actmon_readl(u32 offset)
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{
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return __raw_readl(cpumon->base + offset);
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}
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static inline void actmon_writel(u32 val, u32 offset)
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{
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__raw_writel(val, cpumon->base + offset);
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}
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static inline void actmon_wmb(void)
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{
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wmb();
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}
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static irqreturn_t adsp_cpustat_isr(int irq, void *dev_id)
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{
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u32 val;
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unsigned long period, flags;
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spin_lock_irqsave(&cpumon->lock, flags);
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val = actmon_readl(ACTMON_DEV_INTR_STATUS);
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actmon_writel(val, ACTMON_DEV_INTR_STATUS);
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if (val & ACTMON_DEV_INTR_AT_END) {
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period = (255 * SAMPLE_MS_DIVIDER) / cpumon->ape_freq;
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cpumon->cur_usage =
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((u64)actmon_readl(ACTMON_DEV_COUNT) * 100) / (period * cpumon->adsp_freq);
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if (cpumon->cur_usage > cpumon->max_usage)
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cpumon->max_usage = cpumon->cur_usage;
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}
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spin_unlock_irqrestore(&cpumon->lock, flags);
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return IRQ_HANDLED;
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}
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static void configure_actmon(void)
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{
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u32 val;
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/* Set countb weight to 256 */
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actmon_writel(0x100, ACTMON_DEV_COUNT_WEGHT);
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/* Enable periodic sampling */
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val = actmon_readl(ACTMON_DEV_CTRL);
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val |= ACTMON_DEV_CTRL_PERIODIC_ENB;
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/* Set sampling period to max i,e, 255 ape clks */
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val &= ~ACTMON_DEV_CTRL_SAMPLE_PERIOD_MASK;
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val |= (0xFF <<
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ACTMON_DEV_CTRL_SAMPLE_PERIOD_VAL_SHIFT)
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& ACTMON_DEV_CTRL_SAMPLE_PERIOD_MASK;
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/* Enable the AT_END interrupt */
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val |= ACTMON_DEV_CTRL_AT_END_ENB;
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actmon_writel(val, ACTMON_DEV_CTRL);
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actmon_writel(ACTMON_DEV_SAMPLE_CTRL_TICK_65536,
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ACTMON_DEV_SAMPLE_CTRL);
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actmon_wmb();
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}
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static void adsp_cpustat_enable(void)
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{
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&cpumon->lock, flags);
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val = actmon_readl(ACTMON_DEV_CTRL);
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val |= ACTMON_DEV_CTRL_ENB;
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actmon_writel(val, ACTMON_DEV_CTRL);
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actmon_wmb();
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enable_irq(cpumon->irq);
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spin_unlock_irqrestore(&cpumon->lock, flags);
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}
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static void adsp_cpustat_disable(void)
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{
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u32 val;
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unsigned long flags;
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spin_lock_irqsave(&cpumon->lock, flags);
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disable_irq(cpumon->irq);
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val = actmon_readl(ACTMON_DEV_CTRL);
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val &= ~ACTMON_DEV_CTRL_ENB;
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actmon_writel(val, ACTMON_DEV_CTRL);
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actmon_writel(0xffffffff, ACTMON_DEV_INTR_STATUS);
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actmon_wmb();
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spin_unlock_irqrestore(&cpumon->lock, flags);
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}
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#define RW_MODE (S_IWUSR | S_IRUSR)
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#define RO_MODE S_IRUSR
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static int cur_usage_get(void *data, u64 *val)
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{
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*val = cpumon->cur_usage;
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(cur_usage_fops, cur_usage_get, NULL, "%llu\n");
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static int max_usage_get(void *data, u64 *val)
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{
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*val = cpumon->max_usage;
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(max_usage_fops, max_usage_get, NULL, "%llu\n");
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static int enable_set(void *data, u64 val)
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{
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if (cpumon->enable == (bool)val)
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return 0;
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cpumon->enable = (bool)val;
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if (cpumon->enable)
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adsp_cpustat_enable();
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else
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adsp_cpustat_disable();
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return 0;
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}
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static int enable_get(void *data, u64 *val)
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{
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*val = cpumon->enable;
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(enable_fops, enable_get, enable_set, "%llu\n");
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static int cpustat_debugfs_init(struct nvadsp_drv_data *drv)
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{
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int ret = -ENOMEM;
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struct dentry *d, *dir;
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if (!drv->adsp_debugfs_root)
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return ret;
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dir = debugfs_create_dir("adsp_cpustat", drv->adsp_debugfs_root);
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if (!dir)
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return ret;
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d = debugfs_create_file(
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"cur_usage", RO_MODE, dir, cpumon, &cur_usage_fops);
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if (!d)
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return ret;
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d = debugfs_create_file(
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"max_usage", RO_MODE, dir, cpumon, &max_usage_fops);
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if (!d)
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return ret;
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d = debugfs_create_file(
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"enable", RW_MODE, dir, cpumon, &enable_fops);
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if (!d)
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return ret;
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return 0;
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}
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int adsp_cpustat_init(struct platform_device *pdev)
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{
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struct nvadsp_drv_data *drv = platform_get_drvdata(pdev);
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static void __iomem *amisc_base;
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u32 val;
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int ret = -EINVAL;
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if (drv->cpustat_initialized)
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return 0;
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cpumon = &cpustat;
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spin_lock_init(&cpumon->lock);
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cpumon->base = drv->base_regs[AMISC] + ACTMON_REG_OFFSET;
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amisc_base = drv->base_regs[AMISC];
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cpumon->ape_clk = clk_get_sys(NULL, "adsp.ape");
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if (IS_ERR_OR_NULL(cpumon->ape_clk)) {
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dev_err(cpumon->device, "Failed to find adsp.ape clk\n");
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ret = -EINVAL;
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goto err_ape_clk;
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}
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ret = clk_prepare_enable(cpumon->ape_clk);
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if (ret) {
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dev_err(cpumon->device, "Failed to enable ape clock\n");
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goto err_ape_enable;
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}
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cpumon->ape_freq = clk_get_rate(cpumon->ape_clk) / 1000;
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cpumon->adsp_clk = clk_get_sys(NULL, "adsp_cpu");
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if (IS_ERR_OR_NULL(cpumon->adsp_clk)) {
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dev_err(cpumon->device, "Failed to find adsp cpu clock\n");
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ret = -EINVAL;
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goto err_adsp_clk;
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}
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ret = clk_prepare_enable(cpumon->adsp_clk);
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if (ret) {
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dev_err(cpumon->device, "Failed to enable adsp cpu clock\n");
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goto err_adsp_enable;
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}
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cpumon->adsp_freq = clk_get_rate(cpumon->adsp_clk) / 1000;
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/* Enable AMISC_ACTMON */
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val = __raw_readl(amisc_base + AMISC_ACTMON_0);
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val |= AMISC_ACTMON_CNT_TARGET_ENABLE;
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__raw_writel(val, amisc_base + AMISC_ACTMON_0);
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/* Clear all interrupts */
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actmon_writel(0xffffffff, ACTMON_DEV_INTR_STATUS);
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/* One time configuration of actmon regs */
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configure_actmon();
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cpumon->irq = drv->agic_irqs[ACTMON_VIRQ];
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ret = request_irq(cpumon->irq, adsp_cpustat_isr,
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IRQ_TYPE_LEVEL_HIGH, "adsp_actmon", cpumon);
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if (ret) {
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dev_err(cpumon->device, "Failed irq %d request\n", cpumon->irq);
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goto err_irq;
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}
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cpustat_debugfs_init(drv);
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drv->cpustat_initialized = true;
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return 0;
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err_irq:
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clk_disable_unprepare(cpumon->adsp_clk);
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err_adsp_enable:
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clk_put(cpumon->adsp_clk);
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err_adsp_clk:
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clk_disable_unprepare(cpumon->ape_clk);
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err_ape_enable:
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clk_put(cpumon->ape_clk);
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err_ape_clk:
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return ret;
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}
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int adsp_cpustat_exit(struct platform_device *pdev)
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{
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status_t ret = 0;
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struct nvadsp_drv_data *drv = platform_get_drvdata(pdev);
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if (!drv->cpustat_initialized) {
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ret = -EINVAL;
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goto end;
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}
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free_irq(cpumon->irq, cpumon);
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clk_disable_unprepare(cpumon->adsp_clk);
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clk_put(cpumon->adsp_clk);
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clk_put(cpumon->ape_clk);
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drv->cpustat_initialized = false;
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end:
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return ret;
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}
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