forked from rrcarlosr/Jetpack
158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
/*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA CORPORATION and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA CORPORATION is strictly prohibited.
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*/
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#ifndef DMCE_PERFMON_H
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#define DMCE_PERFMON_H
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/**
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* Commands used in Command field of an ARI perfmon request.
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*/
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enum DMCE_PERFMON_COMMAND {
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DMCE_PERFMON_COMMAND_READ = 0, /* Read uncore perfmon reg */
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DMCE_PERFMON_COMMAND_WRITE = 1, /* Write uncore perfmon reg */
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DMCE_PERFMON_COMMAND_MAX
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};
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/**
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* Registers used in Register field of an ARI perfmon request.
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*/
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enum DMCE_PERFMON_REGISTER {
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NV_PMEVCNTR = 0,
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NV_PMEVTYPER = 1,
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DMCE_PERFMON_FIRST_UNIT_REGISTER = 2,
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NV_PMCNTENSET = 2,
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NV_PMCNTENCLR = 3,
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NV_PMOVSSET = 4,
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NV_PMOVSCLR = 5,
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NV_PMCR = 6,
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NV_PMINTENSET = 7,
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NV_PMINTENCLR = 8,
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DMCE_PERFMON_FIRST_GROUP_REGISTER = 9,
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NV_PMCRNUNITS = 9,
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NV_PMCEID0 = 10,
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NV_PMCEID1 = 11,
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DMCE_PERFMON_FIRST_GLOBAL_REGISTER = 12,
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NV_AFR0 = 12,
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NV_SECURE = 13,
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DMCE_PERFMON_REGISTER_MAX
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};
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/**
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* Status codes returned in Status field of an ARI perfmon response.
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*/
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enum DMCE_PERFMON_STATUS {
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DMCE_PERFMON_STATUS_SUCCESS = 0,
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DMCE_PERFMON_STATUS_INVALID_GROUP = 1,
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DMCE_PERFMON_STATUS_INVALID_UNIT = 2,
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DMCE_PERFMON_STATUS_INVALID_COUNTER = 3,
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DMCE_PERFMON_STATUS_INVALID_REGISTER = 4,
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DMCE_PERFMON_STATUS_INVALID_COMMAND = 5,
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DMCE_PERFMON_STATUS_READ_ONLY = 6,
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DMCE_PERFMON_STATUS_NOT_SECURE = 7,
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DMCE_PERFMON_STATUS_MAX
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};
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/**
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* Format of the value in ARI_REQUEST_DATA_HI
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* when making an uncore perfmon call.
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*/
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union dmce_perfmon_ari_request_hi_t {
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uint32_t flat;
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struct {
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uint8_t command:8; /* Operation: 0 - read, 1 - write */
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uint8_t group:4; /* Group selector */
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uint8_t unit:4; /* Unit selector */
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uint8_t reg:8; /* Register to read or write */
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uint8_t counter:8; /* CNTR num for EVCNTR and EVTYPER */
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} bits;
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};
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/**
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* Format of the value returned in ARI_RESPONSE_DATA_HI
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* returned by an uncore perfmon call.
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*/
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union dmce_perfmon_ari_response_hi_t {
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uint32_t flat;
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struct {
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uint8_t status:8; /* Resulting command statue */
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uint32_t unused:24;
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} bits;
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};
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/**
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* Layout of the uncore perfmon NV_PMEVTYPER register.
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*/
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union dmce_perfmon_pmevtyper_t {
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uint32_t flat;
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struct {
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uint32_t evt_count:10; /* Event number to count */
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uint32_t reserved_15_10:6;
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uint32_t int_core:4; /* Core to handle interrupt */
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uint32_t reserved_31_20:12;
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} bits;
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};
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/**
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* Layout of the NV_PMCR register.
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*/
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union dmce_perfmon_pmcr_t {
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uint32_t flat;
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struct {
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uint32_t e:1; /* Enable counters */
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uint32_t p:1; /* Reset counters (WO bit) */
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uint32_t reserved_10_2:9;
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uint32_t n:5; /* Number of counters (RO bit)*/
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uint32_t idcode:8; /* Identification code (0) */
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uint32_t imp:8; /* Implementor code ('N') */
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} bits;
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};
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/**
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* Data for each uncore perfmon counter
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*/
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struct dmce_perfmon_cnt_info {
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uint8_t counter; /* Event id */
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uint8_t group; /* Group selector */
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uint8_t unit; /* Unit selector */
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uint8_t index; /* Virtual Index */
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uint8_t idx; /* Physical Index */
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uint8_t valid; /* Valid info */
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};
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typedef enum {
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ACTLR_EL3,
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CPSR,
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NV_PMCCFILTR_EL0,
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NV_PMCCNTR_EL0,
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NV_PMCEID0_EL0,
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NV_PMCEID1_EL0,
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NV_PMCNTENCLR_EL0,
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NV_PMCNTENSET_EL0,
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NV_PMCR_EL0,
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NV_PMCRN_EL0,
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NV_PMINTENCLR_EL1,
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NV_PMINTENSET_EL1,
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NV_PMOVSCLR_EL0,
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NV_PMOVSSET_EL0,
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NV_PMSELR_EL0,
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NV_PMSWINC_EL0,
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NV_PMUSERENR_EL0,
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NV_PMEVCNTR0_EL0,
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NV_PMEVCNTR1_EL0,
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NV_PMEVTYPER0_EL0,
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NV_PMEVTYPER1_EL0,
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NV_PMEVCNTRn_EL0,
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NV_PMEVTYPERn_EL0,
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} carmel_pmc_reg_t;
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#endif
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