forked from rrcarlosr/Jetpack
402 lines
12 KiB
C
402 lines
12 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TEGRA_DVFS_H_
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#define _TEGRA_DVFS_H_
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#include <linux/platform_device.h>
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#include <soc/tegra/cvb.h>
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#define MAX_DVFS_FREQS 40
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#define DVFS_RAIL_STATS_TOP_BIN 200
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#define DVFS_RAIL_STATS_BIN 10000
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#define MAX_THERMAL_LIMITS 8
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#define MAX_THERMAL_RANGES (MAX_THERMAL_LIMITS + 1)
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#define MAX_PROCESS_ID 7
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enum tegra_dvfs_core_thermal_type {
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TEGRA_DVFS_CORE_THERMAL_FLOOR = 0,
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TEGRA_DVFS_CORE_THERMAL_CAP,
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};
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/*
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* dvfs_relationship between to rails, "from" and "to"
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* when the rail changes, it will call dvfs_rail_update on the rails
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* in the relationship_to list.
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* when determining the voltage to set a rail to, it will consider each
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* rail in the relationship_from list.
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*/
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struct dvfs_relationship {
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struct dvfs_rail *to;
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struct dvfs_rail *from;
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int (*solve)(struct dvfs_rail *, struct dvfs_rail *);
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struct list_head to_node; /* node in relationship_to list */
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struct list_head from_node; /* node in relationship_from list */
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bool solved_at_nominal;
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};
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struct cpu_pll_fv_table {
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int freq;
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int volt;
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};
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struct cpu_dvfs {
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int speedo_id;
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int process_id;
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int max_mv;
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int min_mv;
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struct cpu_pll_fv_table fv_table[MAX_DVFS_FREQS];
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int pll_min_millivolts; /* when PLL source is selected */
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int speedo_scale;
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int voltage_scale;
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struct cvb_table_freq_entry cvb_pll_table[MAX_DVFS_FREQS];
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};
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struct rail_stats {
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ktime_t time_at_mv[DVFS_RAIL_STATS_TOP_BIN + 1];
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ktime_t last_update;
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int last_index;
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bool off;
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int bin_uv;
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};
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struct dvfs_therm_limits {
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u32 temperature;
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u32 mv;
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};
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struct dvfs_rail {
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const char *reg_id;
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int min_millivolts;
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int max_millivolts;
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int nominal_millivolts;
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int override_millivolts;
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int dbg_mv_offs;
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int step;
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int step_up;
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bool jmp_to_zero;
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bool disabled;
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bool resolving_to;
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struct list_head node; /* node in dvfs_rail_list */
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struct list_head dvfs; /* list head of attached dvfs clocks */
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struct list_head relationships_to;
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struct list_head relationships_from;
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struct regulator *reg;
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int millivolts;
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int new_millivolts;
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int disable_millivolts;
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int suspend_millivolts;
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bool suspended;
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bool dfll_mode;
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bool joint_rail_with_dfll;
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struct rail_alignment alignment;
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struct rail_stats stats;
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struct dvfs_therm_limits *therm_floors;
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int therm_floors_size;
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int therm_floor_idx;
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bool is_ready;
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bool in_band_pm;
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struct thermal_cooling_device *vts_cdev;
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struct device_node *vts_of_node;
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struct dvfs_therm_limits vts_floors_table[MAX_THERMAL_LIMITS];
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int vts_trips_table[MAX_THERMAL_LIMITS];
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int vts_number_of_trips;
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unsigned long therm_scale_idx;
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struct thermal_cooling_device *vmax_cdev;
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struct device_node *vmax_of_node;
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struct dvfs_therm_limits *therm_caps;
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int therm_caps_size;
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int therm_cap_idx;
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bool therm_cap_warned;
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const char *nvver;
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};
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enum dfll_range {
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DFLL_RANGE_NONE = 0,
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DFLL_RANGE_ALL_RATES,
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DFLL_RANGE_HIGH_RATES,
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};
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struct dvfs {
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const char *clk_name;
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struct clk *clk;
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int speedo_id;
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int process_id;
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int freqs_mult;
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unsigned long freqs[MAX_DVFS_FREQS];
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unsigned long *alt_freqs;
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const int *millivolts;
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const int *peak_millivolts;
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const int *dfll_millivolts;
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struct dvfs_rail *dvfs_rail;
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bool auto_dvfs;
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int max_millivolts;
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int num_freqs;
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enum dfll_range range;
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unsigned long use_dfll_rate_min;
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int cur_millivolts;
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unsigned long cur_rate;
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struct list_head node;
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struct list_head reg_node;
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bool use_alt_freqs;
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bool therm_dvfs;
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bool na_dvfs;
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/* Maximum rate safe at minimum voltage across all thermal ranges */
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unsigned long fmax_at_vmin_safe_t;
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long dbg_hz_offs;
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};
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struct cvb_dvfs_table {
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unsigned long freq;
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/* Coeffs for voltage calculation, when dfll clock source is selected */
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struct cvb_coefficients cvb_dfll_param;
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/* Coeffs for voltage calculation, when pll clock source is selected */
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struct cvb_coefficients cvb_pll_param;
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};
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struct cvb_dvfs {
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int speedo_id;
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int process_id;
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/* tuning parameters for pll clock */
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int pll_min_millivolts;
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/* dvfs Max voltage */
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int max_mv;
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/* dvfs Max frequency */
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unsigned long max_freq;
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int freqs_mult;
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/* scaling values for voltage calculation */
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int speedo_scale;
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int voltage_scale;
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int thermal_scale;
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struct cvb_dvfs_table cvb_vmin;
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/* CVB table for various frequencies */
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struct cvb_dvfs_table cvb_table[MAX_DVFS_FREQS];
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const char *cvb_version;
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};
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struct dvb_dvfs_table {
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unsigned long freq;
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int mvolts[MAX_PROCESS_ID + 1];
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};
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struct dvb_dvfs {
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int speedo_id;
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int freqs_mult;
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struct dvb_dvfs_table dvb_table[MAX_DVFS_FREQS];
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};
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static inline bool tegra_dvfs_rail_is_dfll_mode(struct dvfs_rail *rail)
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{
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return rail ? rail->dfll_mode : false;
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}
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static inline bool tegra_dvfs_is_dfll_range_entry(struct dvfs *d,
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unsigned long rate)
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{
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return d->cur_rate && d->dvfs_rail && (!d->dvfs_rail->dfll_mode) &&
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(d->range == DFLL_RANGE_HIGH_RATES) &&
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(rate >= d->use_dfll_rate_min) &&
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(d->cur_rate < d->use_dfll_rate_min);
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}
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static inline bool tegra_dvfs_is_dfll_scale(struct dvfs *d, unsigned long rate)
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{
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return tegra_dvfs_rail_is_dfll_mode(d->dvfs_rail) ||
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tegra_dvfs_is_dfll_range_entry(d, rate);
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}
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static inline bool dvfs_is_dfll_range(struct dvfs *d, unsigned long rate)
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{
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return (d->range == DFLL_RANGE_ALL_RATES) ||
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((d->range == DFLL_RANGE_HIGH_RATES) &&
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(rate >= d->use_dfll_rate_min));
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}
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#ifdef CONFIG_TEGRA_DVFS
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int tegra_dvfs_dfll_mode_set(struct clk *c, unsigned long rate);
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int tegra_dvfs_dfll_mode_clear(struct clk *c, unsigned long rate);
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int tegra_dvfs_get_dfll_threshold(struct clk *c, unsigned long *rate);
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int tegra_dvfs_set_rate(struct clk *c, unsigned long rate);
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unsigned long tegra_dvfs_get_rate(struct clk *c);
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int tegra_dvfs_get_freqs(struct clk *c, unsigned long **freqs, int *num_freqs);
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int tegra_setup_dvfs(struct clk *c, struct dvfs *d);
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int tegra_dvfs_init_rails(struct dvfs_rail *dvfs_rails[], int n);
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void tegra_dvfs_init_rails_lists(struct dvfs_rail *rails[], int n);
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void tegra_dvfs_add_relationships(struct dvfs_relationship *rels, int n);
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void tegra_dvfs_rail_enable(struct dvfs_rail *rail);
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void tegra_dvfs_rail_disable(struct dvfs_rail *rail);
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int tegra_dvfs_predict_millivolts(struct clk *c, unsigned long rate);
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bool tegra_dvfs_is_dfll_range(struct clk *c, unsigned long rate);
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int tegra_dvfs_set_dfll_range(struct clk *c, int range);
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int tegra_get_cpu_fv_table(int *num_freqs, unsigned long **freqs, int **mvs);
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void tegra_dvfs_core_init_therm_limits(struct dvfs_rail *rail);
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int tegra_dvfs_core_get_thermal_index(enum tegra_dvfs_core_thermal_type type);
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int
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tegra_dvfs_core_count_thermal_states(enum tegra_dvfs_core_thermal_type type);
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int tegra_dvfs_core_update_thermal_index(enum tegra_dvfs_core_thermal_type type,
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unsigned long new_idx);
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int tegra_dvfs_core_set_thermal_cap(struct clk *cap_clk,
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unsigned long thermal_index);
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unsigned long tegra_dvfs_get_maxrate(struct clk *c);
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struct dvfs_rail *tegra_dvfs_get_rail_by_name(char *name);
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bool tegra_dvfs_is_rail_up(struct dvfs_rail *rail);
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int tegra_dvfs_rail_power_down(struct dvfs_rail *rail);
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int tegra_dvfs_rail_power_up(struct dvfs_rail *rail);
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unsigned long tegra_dvfs_round_rate(struct clk *c, unsigned long rate);
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int tegra_dvfs_add_alt_freqs(struct clk *c, struct dvfs *d);
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int tegra_dvfs_use_alt_freqs_on_clk(struct clk *c, bool use_alt_freq);
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int tegra_dvfs_predict_mv_at_hz_cur_tfloor(struct clk *c, unsigned long rate);
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int tegra_dvfs_init_thermal_dvfs_voltages(int *therm_voltages,
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int *peak_voltages, int freqs_num, int ranges_num, struct dvfs *d);
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long tegra_dvfs_predict_hz_at_mv_max_tfloor(struct clk *c, int mv);
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int tegra_dvfs_predict_mv_at_hz_max_tfloor(struct clk *c, unsigned long rate);
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unsigned long tegra_dvfs_get_fmax_at_vmin_safe_t(struct clk *c);
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bool tegra_dvfs_is_rail_ready(struct dvfs_rail *rail);
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#else
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static inline int tegra_dvfs_dfll_mode_set(struct clk *c, unsigned long rate)
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{ return -EINVAL; }
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static inline int tegra_dvfs_dfll_mode_clear(struct clk *c, unsigned long rate)
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{ return -EINVAL; }
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static inline int tegra_dvfs_get_dfll_threshold(
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struct clk *c, unsigned long *rate)
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{ return -EINVAL; }
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static inline int tegra_dvfs_set_rate(struct clk *c, unsigned long rate)
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{ return 0; }
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static inline unsigned long tegra_dvfs_get_rate(struct clk *c)
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{ return 0; }
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static inline int tegra_dvfs_get_freqs(
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struct clk *c, unsigned long **freqs, int *num_freqs)
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{ return -EINVAL; }
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static inline int tegra_setup_dvfs(struct clk *c, struct dvfs *d)
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{ return -EINVAL; }
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static inline int tegra_dvfs_init_rails(struct dvfs_rail *dvfs_rails[], int n)
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{ return -EINVAL; }
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static inline void tegra_dvfs_init_rails_lists(struct dvfs_rail *rails[], int n)
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{ return; }
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static inline void tegra_dvfs_add_relationships(
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struct dvfs_relationship *rels, int n)
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{ return; }
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static inline void tegra_dvfs_rail_enable(struct dvfs_rail *rail)
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{ return; }
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static inline void tegra_dvfs_rail_disable(struct dvfs_rail *rail)
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{ return; }
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static inline int tegra_dvfs_predict_millivolts(
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struct clk *c, unsigned long rate)
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{ return -EINVAL; }
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static inline bool tegra_dvfs_is_dfll_range(struct clk *c, unsigned long rate)
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{ return false; }
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static inline int tegra_dvfs_set_dfll_range(struct clk *c, int range)
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{ return -EINVAL; }
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static inline int tegra_get_cpu_fv_table(
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int *num_freqs, unsigned long **freqs, int **mvs)
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{ return -EINVAL; }
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static inline void tegra_dvfs_core_init_therm_limits(struct dvfs_rail *rail)
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{ return; }
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static inline int tegra_dvfs_core_get_thermal_index(
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enum tegra_dvfs_core_thermal_type type)
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{ return -EINVAL; }
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static inline int tegra_dvfs_core_count_thermal_states(
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enum tegra_dvfs_core_thermal_type type)
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{ return -EINVAL; }
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static inline int tegra_dvfs_core_update_thermal_index(
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enum tegra_dvfs_core_thermal_type type,
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unsigned long new_idx)
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{ return -EINVAL; }
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static inline int tegra_dvfs_core_set_thermal_cap(
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struct clk *cap_clk, unsigned long thermal_index)
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{ return -EINVAL; }
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static inline unsigned long tegra_dvfs_get_maxrate(struct clk *c)
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{ return 0; }
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static inline struct dvfs_rail *tegra_dvfs_get_rail_by_name(char *name)
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{ return NULL; }
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static inline bool tegra_dvfs_is_rail_up(struct dvfs_rail *rail)
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{ return false; }
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static inline int tegra_dvfs_rail_power_down(struct dvfs_rail *rail)
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{ return -EINVAL; }
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static inline int tegra_dvfs_rail_power_up(struct dvfs_rail *rail)
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{ return -EINVAL; }
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static inline unsigned long tegra_dvfs_round_rate(struct clk *c,
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unsigned long rate)
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{ return rate; }
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static inline int tegra_dvfs_add_alt_freqs(struct clk *c, struct dvfs *d)
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{ return -EINVAL; }
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static inline int tegra_dvfs_use_alt_freqs_on_clk(struct clk *c,
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bool use_alt_freq)
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{ return -EINVAL; }
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static inline int tegra_dvfs_predict_mv_at_hz_cur_tfloor(struct clk *c,
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unsigned long rate)
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{ return -EINVAL; }
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static inline int tegra_dvfs_init_thermal_dvfs_voltages(int *therm_voltages,
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int *peak_voltages, int freqs_num, int ranges_num, struct dvfs *d)
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{ return -EINVAL; }
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static inline long tegra_dvfs_predict_hz_at_mv_max_tfloor(struct clk *c,
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int mv)
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{ return -EINVAL; }
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static inline int tegra_dvfs_predict_mv_at_hz_max_tfloor(struct clk *c,
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unsigned long rate)
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{ return -EINVAL; }
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static inline unsigned long tegra_dvfs_get_fmax_at_vmin_safe_t(struct clk *c)
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{ return 0; }
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static inline bool tegra_dvfs_is_rail_ready(struct dvfs_rail *rail)
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{ return false; }
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#endif
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#ifdef CONFIG_TEGRA_124_DVFS
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int tegra124_init_dvfs(struct device *node);
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#else
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static inline int tegra124_init_dvfs(struct device *node)
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{ return -EINVAL; }
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#endif
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#ifdef CONFIG_TEGRA_210_DVFS
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int tegra210_init_dvfs(struct device *node);
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int tegra210b01_init_dvfs(struct device *node);
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#else
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static inline int tegra210_init_dvfs(struct device *node)
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{ return -EINVAL; }
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static inline int tegra210b01_init_dvfs(struct device *node)
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{ return -EINVAL; }
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#endif
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#endif
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