forked from rrcarlosr/Jetpack
308 lines
9.0 KiB
C
308 lines
9.0 KiB
C
/*
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* Xilinx xps_ll_temac ethernet driver for u-boot
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*
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* LL_TEMAC interface
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*
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* Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008 - 2011 PetaLogix
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*
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* Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
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* Copyright (C) 2008 Nissin Systems Co.,Ltd.
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* March 2008 created
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [S]: [0]/ip_documentation/xps_ll_temac.pdf
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* [A]: [0]/application_notes/xapp1041.pdf
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*/
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#ifndef _XILINX_LL_TEMAC_
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#define _XILINX_LL_TEMAC_
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#include <config.h>
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#include <net.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <asm/types.h>
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#include <asm/byteorder.h>
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#include "xilinx_ll_temac_sdma.h"
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#if !defined(__BIG_ENDIAN)
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# error LL_TEMAC requires big endianess
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#endif
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/*
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* TEMAC Memory and Register Definition
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*
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* [1]: [0]/ip_documentation/xps_ll_temac.pdf
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* page 19, Memory and Register Descriptions
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*/
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struct temac_reg {
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/* direct soft registers (low part) */
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u32 raf; /* Reset and Address Filter */
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u32 tpf; /* Transmit Pause Frame */
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u32 ifgp; /* Transmit Inter Frame Gap Adjustment */
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u32 is; /* Interrupt Status */
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u32 ip; /* Interrupt Pending */
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u32 ie; /* Interrupt Enable */
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u32 ttag; /* Transmit VLAN Tag */
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u32 rtag; /* Receive VLAN Tag */
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/* hard TEMAC registers */
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u32 msw; /* Most Significant Word Data */
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u32 lsw; /* Least Significant Word Data */
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u32 ctl; /* Control */
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u32 rdy; /* Ready Status */
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/* direct soft registers (high part) */
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u32 uawl; /* Unicast Address Word Lower */
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u32 uawu; /* Unicast Address Word Upper */
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u32 tpid0; /* VLAN TPID Word 0 */
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u32 tpid1; /* VLAN TPID Word 1 */
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};
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/* Reset and Address Filter Registers (raf), [1] p25 */
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#define RAF_SR (1 << 13)
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#define RAF_EMFE (1 << 12)
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#define RAF_NFE (1 << 11)
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#define RAF_RVSTM_POS 9
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#define RAF_RVSTM_MASK (3 << RAF_RVSTM_POS)
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#define RAF_TVSTM_POS 7
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#define RAF_TVSTM_MASK (3 << RAF_TVSTM_POS)
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#define RAF_RVTM_POS 5
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#define RAF_RVTM_MASK (3 << RAF_RVTM_POS)
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#define RAF_TVTM_POS 3
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#define RAF_TVTM_MASK (3 << RAF_TVTM_POS)
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#define RAF_BCREJ (1 << 2)
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#define RAF_MCREJ (1 << 1)
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#define RAF_HTRST (1 << 0)
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/* Transmit Pause Frame Registers (tpf), [1] p28 */
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#define TPF_TPFV_POS 0
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#define TPF_TPFV_MASK (0xFFFF << TPF_TPFV_POS)
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/* Transmit Inter Frame Gap Adjustment Registers (ifgp), [1] p28 */
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#define IFGP_POS 0
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#define IFGP_MASK (0xFF << IFGP_POS)
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/* Interrupt Status, Pending, Enable Registers (is, ip, ie), [1] p29-33 */
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#define ISPE_MR (1 << 7)
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#define ISPE_RDL (1 << 6)
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#define ISPE_TC (1 << 5)
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#define ISPE_RFO (1 << 4)
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#define ISPE_RR (1 << 3)
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#define ISPE_RC (1 << 2)
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#define ISPE_AN (1 << 1)
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#define ISPE_HAC (1 << 0)
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/* Transmit, Receive VLAN Tag Registers (ttag, rtag), [1] p34-35 */
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#define TRTAG_TPID_POS 16
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#define TRTAG_TPID_MASK (0xFFFF << TRTAG_TPID_POS)
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#define TRTAG_PRIO_POS 13
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#define TRTAG_PRIO_MASK (7 << TRTAG_PRIO_POS)
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#define TRTAG_CFI (1 << 12)
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#define TRTAG_VID_POS 0
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#define TRTAG_VID_MASK (0xFFF << TRTAG_VID_POS)
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/* Most, Least Significant Word Data Register (msw, lsw), [1] p46 */
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#define MLSW_POS 0
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#define MLSW_MASK (~0UL << MLSW_POS)
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/* LSW Data Register for PHY addresses (lsw), [1] p66 */
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#define LSW_REGAD_POS 0
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#define LSW_REGAD_MASK (0x1F << LSW_REGAD_POS)
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#define LSW_PHYAD_POS 5
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#define LSW_PHYAD_MASK (0x1F << LSW_PHYAD_POS)
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/* LSW Data Register for PHY data (lsw), [1] p66 */
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#define LSW_REGDAT_POS 0
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#define LSW_REGDAT_MASK (0xFFFF << LSW_REGDAT_POS)
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/* Control Register (ctl), [1] p47 */
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#define CTL_WEN (1 << 15)
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#define CTL_ADDR_POS 0
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#define CTL_ADDR_MASK (0x3FF << CTL_ADDR_POS)
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/* Ready Status Register Ethernet (rdy), [1] p48 */
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#define RSE_HACS_RDY (1 << 14)
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#define RSE_CFG_WR (1 << 6)
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#define RSE_CFG_RR (1 << 5)
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#define RSE_AF_WR (1 << 4)
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#define RSE_AF_RR (1 << 3)
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#define RSE_MIIM_WR (1 << 2)
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#define RSE_MIIM_RR (1 << 1)
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#define RSE_FABR_RR (1 << 0)
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/* Unicast Address Word Lower, Upper Registers (uawl, uawu), [1] p35-36 */
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#define UAWL_UADDR_POS 0
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#define UAWL_UADDR_MASK (~0UL << UAWL_UADDR_POS)
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#define UAWU_UADDR_POS 0
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#define UAWU_UADDR_MASK (0xFFFF << UAWU_UADDR_POS)
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/* VLAN TPID Word 0, 1 Registers (tpid0, tpid1), [1] p37 */
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#define TPID0_V0_POS 0
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#define TPID0_V0_MASK (0xFFFF << TPID0_V0_POS)
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#define TPID0_V1_POS 16
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#define TPID0_V1_MASK (0xFFFF << TPID0_V1_POS)
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#define TPID1_V2_POS 0
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#define TPID1_V2_MASK (0xFFFF << TPID1_V2_POS)
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#define TPID1_V3_POS 16
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#define TPID1_V3_MASK (0xFFFF << TPID1_V3_POS)
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/*
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* TEMAC Indirectly Addressable Register Index Enumeration
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [1]: [0]/ip_documentation/xps_ll_temac.pdf
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* page 23, PLB Indirectly Addressable TEMAC Registers
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*/
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enum temac_ctrl {
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TEMAC_RCW0 = 0x200,
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TEMAC_RCW1 = 0x240,
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TEMAC_TC = 0x280,
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TEMAC_FCC = 0x2C0,
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TEMAC_EMMC = 0x300,
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TEMAC_PHYC = 0x320,
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TEMAC_MC = 0x340,
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TEMAC_UAW0 = 0x380,
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TEMAC_UAW1 = 0x384,
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TEMAC_MAW0 = 0x388,
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TEMAC_MAW1 = 0x38C,
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TEMAC_AFM = 0x390,
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TEMAC_TIS = 0x3A0,
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TEMAC_TIE = 0x3A4,
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TEMAC_MIIMWD = 0x3B0,
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TEMAC_MIIMAI = 0x3B4
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};
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/* Receive Configuration Word 0, 1 Registers (RCW0, RCW1), [1] p50-51 */
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#define RCW0_PADDR_POS 0
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#define RCW0_PADDR_MASK (~0UL << RCW_PADDR_POS)
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#define RCW1_RST (1 << 31)
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#define RCW1_JUM (1 << 30)
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#define RCW1_FCS (1 << 29)
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#define RCW1_RX (1 << 28)
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#define RCW1_VLAN (1 << 27)
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#define RCW1_HD (1 << 26)
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#define RCW1_LT_DIS (1 << 25)
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#define RCW1_PADDR_POS 0
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#define RCW1_PADDR_MASK (0xFFFF << RCW_PADDR_POS)
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/* Transmit Configuration Registers (TC), [1] p52 */
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#define TC_RST (1 << 31)
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#define TC_JUM (1 << 30)
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#define TC_FCS (1 << 29)
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#define TC_TX (1 << 28)
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#define TC_VLAN (1 << 27)
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#define TC_HD (1 << 26)
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#define TC_IFG (1 << 25)
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/* Flow Control Configuration Registers (FCC), [1] p54 */
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#define FCC_FCTX (1 << 30)
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#define FCC_FCRX (1 << 29)
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/* Ethernet MAC Mode Configuration Registers (EMMC), [1] p54 */
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#define EMMC_LSPD_POS 30
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#define EMMC_LSPD_MASK (3 << EMMC_LSPD_POS)
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#define EMMC_LSPD_1000 (2 << EMMC_LSPD_POS)
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#define EMMC_LSPD_100 (1 << EMMC_LSPD_POS)
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#define EMMC_LSPD_10 0
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#define EMMC_RGMII (1 << 29)
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#define EMMC_SGMII (1 << 28)
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#define EMMC_GPCS (1 << 27)
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#define EMMC_HOST (1 << 26)
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#define EMMC_TX16 (1 << 25)
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#define EMMC_RX16 (1 << 24)
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/* RGMII/SGMII Configuration Registers (PHYC), [1] p56 */
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#define PHYC_SLSPD_POS 30
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#define PHYC_SLSPD_MASK (3 << EMMC_SLSPD_POS)
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#define PHYC_SLSPD_1000 (2 << EMMC_SLSPD_POS)
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#define PHYC_SLSPD_100 (1 << EMMC_SLSPD_POS)
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#define PHYC_SLSPD_10 0
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#define PHYC_RLSPD_POS 2
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#define PHYC_RLSPD_MASK (3 << EMMC_RLSPD_POS)
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#define PHYC_RLSPD_1000 (2 << EMMC_RLSPD_POS)
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#define PHYC_RLSPD_100 (1 << EMMC_RLSPD_POS)
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#define PHYC_RLSPD_10 0
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#define PHYC_RGMII_HD (1 << 1)
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#define PHYC_RGMII_LINK (1 << 0)
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/* Management Configuration Registers (MC), [1] p57 */
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#define MC_MDIOEN (1 << 6)
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#define MC_CLKDIV_POS 0
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#define MC_CLKDIV_MASK (0x3F << MC_CLKDIV_POS)
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/*
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* fHOSTCLK fMDC = fHOSTCLK
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* fMDC = ------------------- ---------> MC_CLKDIV = -------- - 1
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* (1 + MC_CLKDIV) * 2 2.5 MHz 5MHz
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*/
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#define MC_CLKDIV(f, m) ((f / (2 * m)) - 1)
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#define MC_CLKDIV_25(f) MC_CLKDIV(f, 2500000)
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#define MC_CLKDIV_20(f) MC_CLKDIV(f, 2000000)
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#define MC_CLKDIV_15(f) MC_CLKDIV(f, 1500000)
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#define MC_CLKDIV_10(f) MC_CLKDIV(f, 1000000)
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/* Unicast Address Word 0, 1 Registers (UAW0, UAW1), [1] p58-59 */
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#define UAW0_UADDR_POS 0
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#define UAW0_UADDR_MASK (~0UL << UAW0_UADDR_POS)
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#define UAW1_UADDR_POS 0
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#define UAW1_UADDR_MASK (0xFFFF << UAW1_UADDR_POS)
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/* Multicast Address Word 0, 1 Registers (MAW0, MAW1), [1] p60 */
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#define MAW0_MADDR_POS 0
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#define MAW0_MADDR_MASK (~0UL << MAW0_MADDR_POS)
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#define MAW1_RNW (1 << 23)
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#define MAW1_MAIDX_POS 16
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#define MAW1_MAIDX_MASK (3 << MAW1_MAIDX_POS)
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#define MAW1_MADDR_POS 0
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#define MAW1_MADDR_MASK (0xFFFF << MAW1_MADDR_POS)
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/* Address Filter Mode Registers (AFM), [1] p63 */
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#define AFM_PM (1 << 31)
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/* Interrupt Status, Enable Registers (TIS, TIE), [1] p63-65 */
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#define TISE_CFG_W (1 << 6)
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#define TISE_CFG_R (1 << 5)
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#define TISE_AF_W (1 << 4)
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#define TISE_AF_R (1 << 3)
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#define TISE_MIIM_W (1 << 2)
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#define TISE_MIIM_R (1 << 1)
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#define TISE_FABR_R (1 << 0)
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/* MII Management Write Data Registers (MIIMWD), [1] p66 */
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#define MIIMWD_DATA_POS 0
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#define MIIMWD_DATA_MASK (0xFFFF << MIIMWD_DATA_POS)
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/* Ethernet interface ready status */
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int ll_temac_check_status(struct temac_reg *regs, u32 mask);
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/* Indirect write to ll_temac. */
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int ll_temac_indirect_set(struct temac_reg *regs, u16 regn, u32 reg_data);
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/* Indirect read from ll_temac. */
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int ll_temac_indirect_get(struct temac_reg *regs, u16 regn, u32* reg_data);
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struct ll_temac {
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phys_addr_t ctrladdr;
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phys_addr_t sdma_reg_addr[SDMA_CTRL_REGNUMS];
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unsigned (*in32)(phys_addr_t);
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void (*out32)(phys_addr_t, unsigned);
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int (*ctrlinit) (struct eth_device *);
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int (*ctrlhalt) (struct eth_device *);
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int (*ctrlreset) (struct eth_device *);
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int phyaddr;
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struct phy_device *phydev;
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struct mii_dev *bus;
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char mdio_busname[MDIO_NAME_LEN];
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};
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#endif /* _XILINX_LL_TEMAC_ */
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