Jetpack/u-boot/arch/arm/cpu/pxa/cache.c
dchvs 31faf4d851 cti_kernel: Add CTI sources
Elroy L4T r32.4.4 – JetPack 4.4.1
2021-03-15 20:15:11 -06:00

63 lines
1.3 KiB
C

/*
* (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/types.h>
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
/* Flush/Invalidate D cache */
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
}
void flush_dcache_all(void)
{
return invalidate_dcache_all();
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
while (start <= stop) {
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
return invalidate_dcache_range(start, stop);
}
#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
/*
* Stub implementations for l2 cache operations
*/
__weak void l2_cache_disable(void) {}
#if defined CONFIG_SYS_THUMB_BUILD
__weak void invalidate_l2_cache(void) {}
#endif