forked from rrcarlosr/Jetpack
83 lines
3.1 KiB
C
83 lines
3.1 KiB
C
/*
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* clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
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* Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
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*
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* Aleksandr Frid <afrid@nvidia.com>
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* Paul Walmsley <pwalmsley@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/types.h>
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#include <soc/tegra/cvb.h>
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#include <soc/tegra/tegra-dfll.h>
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struct thermal_tv;
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/**
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* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
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* @dev: struct device * that holds the OPP table for the DFLL
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* @max_freq: maximum frequency supported on this SoC
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* @cvb: CPU frequency table for this SoC
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* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
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* @tune0_low: DFLL tuning register 0 (low voltage range)
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* @tune0_high: DFLL tuning register 0 (high voltage range)
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* @tune1: DFLL tuning register 1
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* @set_clock_trimmers_high: fn ptr to tune clock trimmers for high voltage
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* @set_clock_trimmers_low: fn ptr to tune clock trimmers for low voltage
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* @thermal_floor_table: table mapping a given temperature to a minimum voltage
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* @thermal_cap_table: table mapping a given temperature to a maximum voltage
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* @thermal_floor_table_size: size of thermal_floor_table
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* @thermal_cap_table_size: size of thermal_cap_table
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*/
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struct tegra_dfll_soc_data {
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struct device *dev;
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unsigned long max_freq;
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const struct cvb_table *cvb;
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struct rail_alignment alignment;
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unsigned int min_millivolts;
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unsigned int tune_high_min_millivolts;
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u32 tune0_low;
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u32 tune0_high;
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u32 tune1_low;
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u32 tune1_high;
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unsigned int tune_high_margin_millivolts;
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void (*init_clock_trimmers)(void);
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void (*set_clock_trimmers_high)(void);
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void (*set_clock_trimmers_low)(void);
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const struct thermal_tv *thermal_floor_table;
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const struct thermal_tv *thermal_cap_table;
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unsigned int thermal_floor_table_size;
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unsigned int thermal_cap_table_size;
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};
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/*
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* These thermal boundaries are not set in thermal zone as trip-points, but
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* must be below/above all other actually set DFLL thermal trip-points.
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*/
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#define DFLL_THERMAL_CAP_NOCAP 0
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#define DFLL_THERMAL_FLOOR_NOFLOOR 125000
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int tegra_dfll_register(struct platform_device *pdev,
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struct tegra_dfll_soc_data *soc);
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struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
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void tegra_dfll_suspend(struct platform_device *pdev);
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void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll);
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int tegra_dfll_resume_tuning(struct device *dev);
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int tegra_dfll_runtime_suspend(struct device *dev);
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int tegra_dfll_runtime_resume(struct device *dev);
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#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */
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