forked from rrcarlosr/Jetpack
205 lines
5.8 KiB
C
205 lines
5.8 KiB
C
/*
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* Copyright (C) 2016-2018, NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef ACTMON_COMMON_H
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#include <asm/io.h>
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/* START: These device register offsets have common value across socs */
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#define ACTMON_CMN_DEV_CTRL 0x00
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#define ACTMON_CMN_DEV_CTRL_ENB (0x1 << 31)
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#define ACTMON_CMN_DEV_CTRL_UP_WMARK_NUM_SHIFT 26
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#define ACTMON_CMN_DEV_CTRL_UP_WMARK_NUM_MASK (0x7 << 26)
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#define ACTMON_CMN_DEV_CTRL_DOWN_WMARK_NUM_SHIFT 21
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#define ACTMON_CMN_DEV_CTRL_DOWN_WMARK_NUM_MASK (0x7 << 21)
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/* Common dev interrupt status bits across socs */
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#define ACTMON_CMN_DEV_INTR_UP_WMARK (0x1 << 31)
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#define ACTMON_CMN_DEV_INTR_DOWN_WMARK (0x1 << 30)
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/* END: common device regs across socs */
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#define ACTMON_DEFAULT_AVG_WINDOW_LOG2 7
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#define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */
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#define ACTMON_DEFAULT_SAMPLING_PERIOD 7
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#define DEFAULT_SUSPEND_FREQ 204000
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#define DEFAULT_BOOST_UP_COEF 200
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#define DEFAULT_BOOST_DOWN_COEF 50
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#define DEFAULT_BOOST_UP_THRESHOLD 30
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#define DEFAULT_BOOST_DOWN_THRESHOLD 20
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#define DEFAULT_UP_WMARK_WINDOW 3
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#define DEFAULT_DOWN_WMARK_WINDOW 2
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#define DEFAULT_EWMA_COEF_K 6
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#define DEFAULT_COUNT_WEIGHT 0x53
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#define FREQ_SAMPLER 1
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#define LOAD_SAMPLER 0
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#define DEFAULT_ACTMON_TYPE FREQ_SAMPLER
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/* Maximum frequency EMC is running at when sourced from PLLP. This is
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* really a short-cut, but it is true for all Tegra3 platforms
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*/
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#define EMC_PLLP_FREQ_MAX 204000
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enum actmon_devices {
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MC_ALL, /* Should match with device sequence in dt */
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MAX_DEVICES,
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};
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enum actmon_type {
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ACTMON_LOAD_SAMPLER,
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ACTMON_FREQ_SAMPLER,
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};
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enum actmon_state {
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ACTMON_UNINITIALIZED = -1,
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ACTMON_OFF = 0,
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ACTMON_ON = 1,
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ACTMON_SUSPENDED = 2,
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};
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struct actmon_dev;
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struct actmon_drv_data;
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struct dev_reg_ops {
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void (*set_init_avg)(u32 value, void __iomem *base);
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void (*set_avg_up_wm)(u32 value, void __iomem *base);
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void (*set_avg_dn_wm)(u32 value, void __iomem *base);
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void (*set_dev_up_wm)(u32 value, void __iomem *base);
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void (*set_dev_dn_wm)(u32 value, void __iomem *base);
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void (*enb_dev_wm)(u32 *value);
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void (*disb_dev_up_wm)(u32 *value);
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void (*disb_dev_dn_wm)(u32 *value);
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void (*set_intr_st)(u32 value, void __iomem *base);
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void (*init_dev_cntrl)(struct actmon_dev *, void __iomem *base);
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void (*enb_dev_intr)(u32 value, void __iomem *base);
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void (*enb_dev_intr_all)(void __iomem *base);
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void (*set_cnt_wt)(u32 value, void __iomem *base);
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u32 (*get_intr_st)(void __iomem *base);
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u32 (*get_dev_intr_enb)(void __iomem *base);
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u32 (*get_dev_intr)(void __iomem *base);
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u32 (*get_raw_cnt)(void __iomem *base);
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u32 (*get_avg_cnt)(void __iomem *base);
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u32 (*get_cum_cnt)(void __iomem *base);
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};
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/* Units:
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* - frequency in kHz
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* - coefficients, and thresholds in %
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* - sampling period in ms
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* - window in sample periods (value = setting + 1)
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*/
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struct actmon_dev {
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struct device_node *dn;
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u32 reg_offs;
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u32 glb_status_irq_mask;
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const char *dev_name;
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const char *con_id;
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void *clnt;
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unsigned long max_freq;
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unsigned long target_freq;
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unsigned long cur_freq;
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unsigned long suspend_freq;
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unsigned long avg_actv_freq;
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unsigned long avg_band_freq;
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unsigned int avg_sustain_coef;
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u32 avg_count;
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u32 avg_dependency_threshold;
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unsigned long boost_freq;
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unsigned long boost_freq_step;
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unsigned int boost_up_coef;
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unsigned int boost_down_coef;
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unsigned int boost_up_threshold;
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unsigned int boost_down_threshold;
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u8 up_wmark_window;
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u8 down_wmark_window;
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u8 avg_window_log2;
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u32 count_weight;
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enum actmon_type type;
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enum actmon_state state;
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enum actmon_state saved_state;
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struct dev_reg_ops ops;
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void (*actmon_dev_set_rate)(struct actmon_dev *, unsigned long);
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unsigned long (*actmon_dev_get_rate)(struct actmon_dev *);
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unsigned long (*actmon_dev_post_change_rate)(struct actmon_dev *,
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void *v);
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void (*actmon_dev_clk_enable)(struct actmon_dev *);
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spinlock_t lock;
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struct notifier_block rate_change_nb;
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struct kobj_attribute avgact_attr;
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};
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struct actmon_reg_ops {
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void (*set_sample_prd)(u32 value, void __iomem *base);
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void (*set_glb_intr)(u32 value, void __iomem *base);
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u32 (*get_glb_intr_st)(void __iomem *base);
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};
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struct actmon_drv_data {
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void __iomem *base;
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struct platform_device *pdev;
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int virq;
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struct clk *actmon_clk;
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u8 sample_period;
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unsigned long freq;
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struct reset_control *actmon_rst;
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struct actmon_dev devices[MAX_DEVICES];
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int (*actmon_dev_platform_init)(struct actmon_dev *adev,
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struct platform_device *pdev);
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int (*clock_init)(struct platform_device *pdev);
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int (*clock_deinit)(struct platform_device *pdev);
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int (*reset_init)(struct platform_device *pdev);
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int (*reset_deinit)(struct platform_device *pdev);
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void (*dev_free_resource)(struct actmon_dev *adev,
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struct platform_device *pdev);
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struct actmon_reg_ops ops;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dfs_root;
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#endif
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struct kobject *actmon_kobj;
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};
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static inline void actmon_wmb(void)
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{
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dsb(sy);
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}
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static inline u32 actmon_dev_readl(void __iomem *base,
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u32 offset)
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{
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return __raw_readl(base + offset);
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}
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static inline void actmon_dev_writel(void __iomem *base, u32
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offset, u32 val)
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{
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__raw_writel(val, base + offset);
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}
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#if defined(CONFIG_TEGRA_CENTRAL_ACTMON)
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int tegra_actmon_register(struct actmon_drv_data *actmon);
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int tegra_actmon_remove(struct platform_device *pdev);
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#else
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static inline int tegra_actmon_register(struct actmon_drv_data *actmon)
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{
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return -EINVAL;
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}
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static inline int tegra_actmon_remove(struct platform_device *pdev)
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{
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return -EINVAL;
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}
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#endif
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#endif /* ACTMON_COMMON_H */
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