forked from rrcarlosr/Jetpack
211 lines
6.2 KiB
Plaintext
211 lines
6.2 KiB
Plaintext
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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#include <dt-bindings/gpio/tegra194-gpio.h>
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/ {
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aliases {
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i2c0 = &gen1_i2c;
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i2c1 = &gen2_i2c;
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i2c2 = &cam_i2c;
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i2c3 = &dp_aux_ch1_i2c;
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i2c4 = &pwr_i2c;
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i2c5 = &dp_aux_ch0_i2c;
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i2c6 = &dp_aux_ch2_i2c;
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i2c7 = &gen8_i2c;
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i2c8 = &dp_aux_ch3_i2c;
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};
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gen1_i2c: i2c@3160000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0x3160000 0x0 0x100>;
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nvidia,hw-instance-id = <0x0>;
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interrupts = <0 TEGRA194_IRQ_I2C1 0x04>;
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scl-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(I, 3) 0>;
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sda-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(I, 4) 0>;
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status = "disabled";
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clock-frequency = <400000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C1
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C1>;
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reset-names = "i2c";
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dmas = <&gpcdma 21>, <&gpcdma 21>;
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dma-names = "rx", "tx";
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};
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gen2_i2c: i2c@c240000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0xc240000 0x0 0x100>;
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nvidia,hw-instance-id = <0x1>;
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interrupts = <0 TEGRA194_IRQ_I2C2 0x04>;
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scl-gpio = <&tegra_aon_gpio TEGRA194_AON_GPIO(CC, 7) 0>;
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sda-gpio = <&tegra_aon_gpio TEGRA194_AON_GPIO(DD, 0) 0>;
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status = "disabled";
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clock-frequency = <100000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C2
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C2>;
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reset-names = "i2c";
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dmas = <&gpcdma 22>, <&gpcdma 22>;
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dma-names = "rx", "tx";
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};
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cam_i2c: i2c@3180000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0x3180000 0x0 0x100>;
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nvidia,hw-instance-id = <0x2>;
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interrupts = <0 TEGRA194_IRQ_I2C3 0x04>;
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scl-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(P, 2) 0>;
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sda-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(P, 3) 0>;
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status = "disabled";
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clock-frequency = <400000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C3
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C3>;
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reset-names = "i2c";
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dmas = <&gpcdma 23>, <&gpcdma 23>;
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dma-names = "rx", "tx";
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};
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dp_aux_ch1_i2c: i2c@3190000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0x3190000 0x0 0x100>;
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nvidia,hw-instance-id = <0x3>;
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interrupts = <0 TEGRA194_IRQ_I2C4 0x04>;
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status = "disabled";
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clock-frequency = <100000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C4
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C4>;
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reset-names = "i2c";
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dmas = <&gpcdma 26>, <&gpcdma 26>;
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dma-names = "rx", "tx";
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};
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pwr_i2c: bpmp_i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra186-bpmp-i2c";
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status = "disabled";
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nvidia,hw-instance-id = <0x4>;
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adapter = <5>;
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};
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dp_aux_ch0_i2c: i2c@31b0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0x31b0000 0x0 0x100>;
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nvidia,hw-instance-id = <0x5>;
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interrupts = <0 TEGRA194_IRQ_I2C6 0x04>;
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status = "disabled";
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clock-frequency = <100000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C6
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C6>;
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reset-names = "i2c";
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dmas = <&gpcdma 30>, <&gpcdma 30>;
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dma-names = "rx", "tx";
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};
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dp_aux_ch2_i2c: i2c@31c0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0x31c0000 0x0 0x100>;
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nvidia,hw-instance-id = <0x6>;
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interrupts = <0 TEGRA194_IRQ_I2C7 0x04>;
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status = "disabled";
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clock-frequency = <100000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C7
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C7>;
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reset-names = "i2c";
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dmas = <&gpcdma 27>, <&gpcdma 27>;
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dma-names = "rx", "tx";
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};
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gen8_i2c: i2c@c250000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0xc250000 0x0 0x100>;
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nvidia,hw-instance-id = <0x7>;
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interrupts = <0 TEGRA194_IRQ_I2C8 0x04>;
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scl-gpio = <&tegra_aon_gpio TEGRA194_AON_GPIO(DD, 1) 0>;
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sda-gpio = <&tegra_aon_gpio TEGRA194_AON_GPIO(DD, 2) 0>;
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status = "disabled";
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clock-frequency = <400000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C8
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C8>;
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reset-names = "i2c";
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dmas = <&gpcdma 0>, <&gpcdma 0>;
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dma-names = "rx", "tx";
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};
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dp_aux_ch3_i2c: i2c@31e0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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compatible = "nvidia,tegra194-i2c";
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reg = <0x0 0x31e0000 0x0 0x100>;
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nvidia,hw-instance-id = <0x8>;
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interrupts = <0 TEGRA194_IRQ_I2C9 0x04>;
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status = "disabled";
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clock-frequency = <100000>;
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clocks = <&bpmp_clks TEGRA194_CLK_I2C9
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&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "div-clk", "parent";
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resets = <&bpmp_resets TEGRA194_RESET_I2C9>;
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reset-names = "i2c";
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dmas = <&gpcdma 31>, <&gpcdma 31>;
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dma-names = "rx", "tx";
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};
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};
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