forked from rrcarlosr/Jetpack
165 lines
4.2 KiB
C
165 lines
4.2 KiB
C
/*
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* U-Boot - Configuration file for CSP Minotaur board
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*
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* Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
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* Minotaur config, brushed up for official uClinux dist.
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* Parallel flash support disabled, SPI flash boot command
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* added ('run flashboot').
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*
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* Flash image map:
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*
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* 0x00000000 u-boot bootstrap
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* 0x00010000 environment
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* 0x00020000 u-boot code
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* 0x00030000 uImage.initramfs
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*
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*/
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#ifndef __CONFIG_BF537_SRV1_H__
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#define __CONFIG_BF537_SRV1_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf537-0.2
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 22118400
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 20
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_SIZE 32
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#define CONFIG_MEM_ADD_WDTH 9
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#define CONFIG_EBIU_SDRRC_VAL 0x2ac
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#define CONFIG_EBIU_SDGCTL_VAL 0x91110d
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_SYS_MALLOC_LEN (384 << 10)
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/*
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* Network Settings
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*/
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#ifndef __ADSPBF534__
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#define CONFIG_BFIN_MAC
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#define CONFIG_NETCONSOLE 1
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#endif
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#ifdef CONFIG_BFIN_MAC
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#define CONFIG_IPADDR 192.168.0.15
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_GATEWAYIP 192.168.0.1
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#define CONFIG_SERVERIP 192.168.0.2
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#define CONFIG_HOSTNAME bf537-srv1
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#endif
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#define CONFIG_SYS_AUTOLOAD "no"
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#define CONFIG_ROOTPATH "/romfs"
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/*
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* Flash Settings
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*/
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/* We don't have a parallel flash chip there */
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#define CONFIG_SYS_NO_FLASH
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/*
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* SPI Settings
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*/
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#define CONFIG_BFIN_SPI
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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/*
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* Env Storage Settings
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*/
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
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/*
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* I2C settings
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_ADI
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0
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/*
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* Misc Settings
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*/
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_BFIN_SERIAL
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#define CONFIG_PANIC_HANG 1
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#define CONFIG_RTC_BFIN 1
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#define CONFIG_BOOT_RETRY_TIME -1
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#define CONFIG_LOADS_ECHO 1
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#define CONFIG_CMD_BOOTLDR
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#define CONFIG_CMD_DATE
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#define CONFIG_BOOTCOMMAND "run flashboot"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
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#define BOOT_ENV_SETTINGS \
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"update=tftpboot $(loadaddr) u-boot.ldr;" \
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"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
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"sf erase 0 0x30000;" \
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"sf write $(loadaddr) 0 $(filesize)" \
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"flashboot=sf read 0x1000000 0x30000 0x320000;" \
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"bootm 0x1000000\0"
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#ifdef CONFIG_BFIN_MAC
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# define NETWORK_ENV_SETTINGS \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath)\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname):eth0:off\0" \
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"ramboot=tftpboot $(loadaddr) linux;" \
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"run ramargs;run addip;bootelf\0" \
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"nfsboot=tftpboot $(loadaddr) linux;" \
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"run nfsargs;run addip;bootelf\0"
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#else
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# define NETWORK_ENV_SETTINGS
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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NETWORK_ENV_SETTINGS \
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"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
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BOOT_ENV_SETTINGS
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#endif
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