forked from rrcarlosr/Jetpack
215 lines
4.5 KiB
C
215 lines
4.5 KiB
C
/*
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* (C) Copyright 2010
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* ISEE 2007 SL, <www.iseebcn.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <status_led.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <twl4030.h>
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#include <netdev.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include "igep00x0.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NET)
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/* GPMC definitions for LAN9221 chips */
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static const u32 gpmc_lan_config[] = {
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NET_LAN9221_GPMC_CONFIG1,
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NET_LAN9221_GPMC_CONFIG2,
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NET_LAN9221_GPMC_CONFIG3,
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NET_LAN9221_GPMC_CONFIG4,
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NET_LAN9221_GPMC_CONFIG5,
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NET_LAN9221_GPMC_CONFIG6,
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};
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#endif
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static const struct ns16550_platdata igep_serial = {
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.base = OMAP34XX_UART3,
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.reg_shift = 2,
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.clock = V_NS16550_CLK
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};
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U_BOOT_DEVICE(igep_uart) = {
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"ns16550_serial",
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&igep_serial
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};
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: omap_rev_string
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* Description: For SPL builds output board rev
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*/
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void omap_rev_string(void)
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{
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}
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->mr = MICRON_V_MR_165;
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#ifdef CONFIG_BOOT_NAND
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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#else
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if (get_cpu_family() == CPU_OMAP34XX) {
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timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
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timings->ctrla = NUMONYX_V_ACTIMA_165;
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timings->ctrlb = NUMONYX_V_ACTIMB_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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} else {
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timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
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timings->ctrla = NUMONYX_V_ACTIMA_200;
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timings->ctrlb = NUMONYX_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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}
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#endif
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}
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#endif
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#if defined(CONFIG_CMD_NET)
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static void reset_net_chip(int gpio)
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{
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if (!gpio_request(gpio, "eth nrst")) {
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gpio_direction_output(gpio, 1);
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udelay(1);
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gpio_set_value(gpio, 0);
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udelay(40);
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gpio_set_value(gpio, 1);
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mdelay(10);
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}
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}
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/*
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* Routine: setup_net_chip
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* Description: Setting up the configuration GPMC registers specific to the
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* Ethernet hardware.
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*/
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static void setup_net_chip(void)
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{
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
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writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
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/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
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/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
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writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
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&ctrl_base->gpmc_nadv_ale);
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reset_net_chip(64);
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}
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#else
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static inline void setup_net_chip(void) {}
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#endif
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_GENERIC_MMC)
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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void set_fdt(void)
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{
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switch (gd->bd->bi_arch_number) {
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case MACH_TYPE_IGEP0020:
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setenv("fdtfile", "omap3-igep0020.dtb");
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break;
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case MACH_TYPE_IGEP0030:
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setenv("fdtfile", "omap3-igep0030.dtb");
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break;
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}
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}
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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twl4030_power_init();
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setup_net_chip();
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omap_die_id_display();
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set_fdt();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_DEFAULT();
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
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MUX_IGEP0020();
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#endif
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#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
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MUX_IGEP0030();
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#endif
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}
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#if defined(CONFIG_CMD_NET)
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SMC911X
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return smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#else
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return 0;
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#endif
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}
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#endif
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