forked from rrcarlosr/Jetpack
603 lines
17 KiB
C
603 lines
17 KiB
C
/*
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* tegra210_afc_alt.c - Tegra210 AFC driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_device.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra210_afc_alt.h"
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#define DRV_NAME "tegra210-afc"
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static const struct reg_default tegra210_afc_reg_defaults[] = {
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{ TEGRA210_AFC_AXBAR_RX_CIF_CTRL, 0x00007700},
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{ TEGRA210_AFC_AXBAR_TX_INT_MASK, 0x00000001},
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{ TEGRA210_AFC_AXBAR_TX_CIF_CTRL, 0x00007000},
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{ TEGRA210_AFC_CG, 0x1},
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{ TEGRA210_AFC_INT_MASK, 0x1},
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{ TEGRA210_AFC_DEST_I2S_PARAMS, 0x01190e0c },
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{ TEGRA210_AFC_TXCIF_FIFO_PARAMS, 0x00190e0c },
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{ TEGRA210_AFC_CLK_PPM_DIFF, 0x0000001e},
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{ TEGRA210_AFC_LCOEF_1_4_0, 0x0000002e},
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{ TEGRA210_AFC_LCOEF_1_4_1, 0x0000f9e6},
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{ TEGRA210_AFC_LCOEF_1_4_2, 0x000020ca},
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{ TEGRA210_AFC_LCOEF_1_4_3, 0x00007147},
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{ TEGRA210_AFC_LCOEF_1_4_4, 0x0000f17e},
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{ TEGRA210_AFC_LCOEF_1_4_5, 0x000001e0},
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{ TEGRA210_AFC_LCOEF_2_4_0, 0x00000117},
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{ TEGRA210_AFC_LCOEF_2_4_1, 0x0000f26b},
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{ TEGRA210_AFC_LCOEF_2_4_2, 0x00004c07},
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};
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static void tegra210_afc_init(struct tegra210_afc *afc)
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{
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afc->ppm_diff = AFC_CLK_PPM_DIFF;
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afc->threshold_type = TH_DEFAULT;
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afc->src_burst = 0;
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afc->start_threshold = 0;
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afc->dest_module_num = 0;
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}
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static int tegra210_afc_runtime_suspend(struct device *dev)
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{
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struct tegra210_afc *afc = dev_get_drvdata(dev);
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regcache_cache_only(afc->regmap, true);
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regcache_mark_dirty(afc->regmap);
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return 0;
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}
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static int tegra210_afc_runtime_resume(struct device *dev)
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{
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struct tegra210_afc *afc = dev_get_drvdata(dev);
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regcache_cache_only(afc->regmap, false);
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regcache_sync(afc->regmap);
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return 0;
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}
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static int tegra210_afc_controls_get(struct snd_kcontrol *kctl,
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struct snd_ctl_elem_value *uctl)
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{
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kctl);
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struct tegra210_afc *afc = snd_soc_codec_get_drvdata(codec);
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if (strstr(kctl->id.name, "ppm diff"))
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uctl->value.integer.value[0] = afc->ppm_diff;
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else if (strstr(kctl->id.name, "src burst"))
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uctl->value.integer.value[0] = afc->src_burst;
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else if (strstr(kctl->id.name, "start threshold"))
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uctl->value.integer.value[0] = afc->start_threshold;
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else if (strstr(kctl->id.name, "threshold type"))
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uctl->value.integer.value[0] = afc->threshold_type;
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else if (strstr(kctl->id.name, "dest module name"))
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uctl->value.integer.value[0] = afc->dest_module_num;
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return 0;
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}
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static int tegra210_afc_controls_put(struct snd_kcontrol *kctl,
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struct snd_ctl_elem_value *uctl)
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{
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kctl);
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struct tegra210_afc *afc = snd_soc_codec_get_drvdata(codec);
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int value = uctl->value.integer.value[0];
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if (strstr(kctl->id.name, "ppm diff")) {
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if (value >= 0 && value <= 100)
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afc->ppm_diff = value;
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else
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return -EINVAL;
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} else if (strstr(kctl->id.name, "src burst")) {
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if (value >= 0 && value <= 24)
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afc->src_burst = value;
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else
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return -EINVAL;
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} else if (strstr(kctl->id.name, "start threshold")) {
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if (value >= 0 && value <= 63)
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afc->start_threshold = value;
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else
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return -EINVAL;
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} else if (strstr(kctl->id.name, "dest module name"))
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afc->dest_module_num = value;
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else if (strstr(kctl->id.name, "threshold type"))
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afc->threshold_type = value;
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return 0;
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}
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static const char *const tegra210_afc_threshold_type_text[] = {
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"None", "NO-SFC", "SFC", "SFC-AMX",
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};
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static const char *const tegra186_afc_dst_mod_type_text[] = {
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"None", "I2S1", "I2S2", "I2S3", "I2S4", "I2S5",
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"I2S6", "DSPK1", "DSPK2",
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};
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static const char *const tegra210_afc_dst_mod_type_text[] = {
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"None", "I2S1", "I2S2", "I2S3", "I2S4", "I2S5",
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};
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static const struct soc_enum tegra210_afc_threshold_config_enum =
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tegra210_afc_threshold_type_text),
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tegra210_afc_threshold_type_text);
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static const struct soc_enum tegra210_afc_dst_mod_type_enum =
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tegra210_afc_dst_mod_type_text),
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tegra210_afc_dst_mod_type_text);
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static const struct soc_enum tegra186_afc_dst_mod_type_enum =
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tegra186_afc_dst_mod_type_text),
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tegra186_afc_dst_mod_type_text);
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#define NV_SOC_SINGLE_RANGE_EXT(xname, xmin, xmax, xget, xput) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
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.info = snd_soc_info_xr_sx, .get = xget, .put = xput, \
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.private_value = (unsigned long)&(struct soc_mixer_control) \
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{.invert = 0, .min = xmin, .max = xmax, \
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.platform_max = xmax}}
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static const struct snd_kcontrol_new tegra210_afc_controls[] = {
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NV_SOC_SINGLE_RANGE_EXT("ppm diff", 0, 100, tegra210_afc_controls_get,
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tegra210_afc_controls_put),
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NV_SOC_SINGLE_RANGE_EXT("src burst", 0, 24, tegra210_afc_controls_get,
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tegra210_afc_controls_put),
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NV_SOC_SINGLE_RANGE_EXT("start threshold", 0, 63,
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tegra210_afc_controls_get, tegra210_afc_controls_put),
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SOC_ENUM_EXT("threshold type", tegra210_afc_threshold_config_enum,
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tegra210_afc_controls_get, tegra210_afc_controls_put),
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SOC_ENUM_EXT("dest module name", tegra210_afc_dst_mod_type_enum,
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tegra210_afc_controls_get, tegra210_afc_controls_put),
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};
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static const struct snd_kcontrol_new tegra186_afc_controls[] = {
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NV_SOC_SINGLE_RANGE_EXT("ppm diff", 0, 100, tegra210_afc_controls_get,
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tegra210_afc_controls_put),
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NV_SOC_SINGLE_RANGE_EXT("src burst", 0, 24, tegra210_afc_controls_get,
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tegra210_afc_controls_put),
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NV_SOC_SINGLE_RANGE_EXT("start threshold", 0, 63,
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tegra210_afc_controls_get, tegra210_afc_controls_put),
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SOC_ENUM_EXT("threshold type", tegra210_afc_threshold_config_enum,
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tegra210_afc_controls_get, tegra210_afc_controls_put),
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SOC_ENUM_EXT("dest module name", tegra186_afc_dst_mod_type_enum,
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tegra210_afc_controls_get, tegra210_afc_controls_put),
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};
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static int tegra210_afc_set_thresholds(struct tegra210_afc *afc,
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unsigned int afc_id)
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{
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unsigned int val_afc, val_dst_mod, dest_module, dest_module_id;
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if (afc->dest_module_num == 0) {
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pr_err("destination module for afc not selected\n");
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return -EINVAL;
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}
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if (afc->dest_module_num > afc->soc_data->num_i2s) {
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dest_module = 1;
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dest_module_id = afc->dest_module_num - afc->soc_data->num_i2s;
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} else {
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dest_module = 0;
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dest_module_id = afc->dest_module_num;
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}
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switch (afc->threshold_type) {
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case TH_NON_SFC:
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if (afc->start_threshold == 0) {
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pr_err("case %s: threshold not defined\n",
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tegra210_afc_threshold_type_text[TH_NON_SFC]);
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goto err_exit;
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}
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val_afc = (afc->start_threshold + 1) <<
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TEGRA210_AFC_FIFO_HIGH_THRESHOLD_SHIFT;
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val_afc |= afc->start_threshold <<
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TEGRA210_AFC_FIFO_START_THRESHOLD_SHIFT;
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val_afc |= afc->start_threshold - 1;
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val_dst_mod = val_afc;
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break;
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/* use src_burst when SFC is in the path*/
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case TH_SFC:
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if (afc->src_burst == 0) {
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pr_err("case %s: src_burst not defined\n",
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tegra210_afc_threshold_type_text[TH_SFC]);
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goto err_exit;
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}
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val_afc = (afc->src_burst + 1) <<
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TEGRA210_AFC_FIFO_HIGH_THRESHOLD_SHIFT;
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val_afc |= (afc->src_burst + 1) <<
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TEGRA210_AFC_FIFO_START_THRESHOLD_SHIFT;
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val_afc |= afc->src_burst + 1;
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val_dst_mod = ((afc->src_burst << 1) + 1) <<
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TEGRA210_AFC_FIFO_HIGH_THRESHOLD_SHIFT;
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val_dst_mod |= (afc->src_burst + 2) <<
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TEGRA210_AFC_FIFO_START_THRESHOLD_SHIFT;
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val_dst_mod |= afc->src_burst;
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break;
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case TH_SFC_AMX:
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if (afc->src_burst == 0) {
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pr_err("case %s: src_burst not defined\n",
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tegra210_afc_threshold_type_text[TH_SFC_AMX]);
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goto err_exit;
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}
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val_afc = ((afc->src_burst << 1) + 4) <<
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TEGRA210_AFC_FIFO_HIGH_THRESHOLD_SHIFT;
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val_afc |= (afc->src_burst + 4) <<
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TEGRA210_AFC_FIFO_START_THRESHOLD_SHIFT;
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val_afc |= 4;
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val_dst_mod = ((afc->src_burst << 1) + 1) <<
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TEGRA210_AFC_FIFO_HIGH_THRESHOLD_SHIFT;
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val_dst_mod |= (afc->src_burst + 2) <<
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TEGRA210_AFC_FIFO_START_THRESHOLD_SHIFT;
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val_dst_mod |= afc->src_burst;
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break;
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/* default threshold settings */
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case TH_DEFAULT:
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val_afc = 4 << TEGRA210_AFC_FIFO_HIGH_THRESHOLD_SHIFT;
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val_afc |= 3 << TEGRA210_AFC_FIFO_START_THRESHOLD_SHIFT;
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val_afc |= 2;
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val_dst_mod = val_afc;
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break;
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default:
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pr_err("unsupported threshold type\n");
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goto err_exit;
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}
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regmap_write(afc->regmap, TEGRA210_AFC_TXCIF_FIFO_PARAMS, val_afc);
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if (afc->soc_data->flag_module_select)
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val_dst_mod |= dest_module << TEGRA186_AFC_MODULE_SELECT_SHIFT;
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val_dst_mod |= dest_module_id << TEGRA210_AFC_DEST_MODULE_ID_SHIFT;
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regmap_write(afc->regmap, TEGRA210_AFC_DEST_I2S_PARAMS, val_dst_mod);
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return 0;
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err_exit:
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return -EINVAL;
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}
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static int tegra210_afc_set_audio_cif(struct tegra210_afc *afc,
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struct snd_pcm_hw_params *params,
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unsigned int reg)
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{
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int channels, audio_bits;
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struct tegra210_xbar_cif_conf cif_conf;
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memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf));
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channels = params_channels(params);
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if (channels < 2)
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return -EINVAL;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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cif_conf.audio_channels = channels;
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cif_conf.client_channels = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra210_xbar_set_cif(afc->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_afc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra210_afc *afc = snd_soc_dai_get_drvdata(dai);
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int ret;
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/* set RX cif and TX cif */
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ret = tegra210_afc_set_audio_cif(afc, params,
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TEGRA210_AFC_AXBAR_RX_CIF_CTRL);
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if (ret) {
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dev_err(dev, "Can't set AFC RX CIF: %d\n", ret);
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return ret;
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}
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ret = tegra210_afc_set_audio_cif(afc, params,
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TEGRA210_AFC_AXBAR_TX_CIF_CTRL);
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if (ret) {
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dev_err(dev, "Can't set AFC TX CIF: %d\n", ret);
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return ret;
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}
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/* update expected ppm difference */
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regmap_update_bits(afc->regmap,
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TEGRA210_AFC_CLK_PPM_DIFF, 0xFFFF, afc->ppm_diff);
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/* program thresholds, dest module depending on the mode*/
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if (tegra210_afc_set_thresholds(afc, dev->id) == -EINVAL)
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dev_err(dev, "Can't set AFC threshold: %d\n", ret);
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return ret;
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}
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static struct snd_soc_dai_ops tegra210_afc_dai_ops = {
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.hw_params = tegra210_afc_hw_params,
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};
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static struct snd_soc_dai_driver tegra210_afc_dais[] = {
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{
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.name = "AFC IN",
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.playback = {
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.stream_name = "AFC Receive",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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},
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{
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.name = "AFC OUT",
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.capture = {
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.stream_name = "AFC Transmit",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_96000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.ops = &tegra210_afc_dai_ops,
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}
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};
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static const struct snd_soc_dapm_widget tegra210_afc_widgets[] = {
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SND_SOC_DAPM_AIF_IN("AFC RX", NULL, 0, SND_SOC_NOPM,
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0, 0),
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SND_SOC_DAPM_AIF_OUT("AFC TX", NULL, 0, TEGRA210_AFC_ENABLE,
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TEGRA210_AFC_EN_SHIFT, 0),
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};
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static const struct snd_soc_dapm_route tegra210_afc_routes[] = {
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{ "AFC RX", NULL, "AFC Receive" },
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{ "AFC TX", NULL, "AFC RX" },
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{ "AFC Transmit", NULL, "AFC TX" },
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};
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static const struct snd_soc_codec_driver tegra210_afc_codec = {
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.idle_bias_off = 1,
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.component_driver = {
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.dapm_widgets = tegra210_afc_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_afc_widgets),
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.dapm_routes = tegra210_afc_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_afc_routes),
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},
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};
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static const struct snd_soc_codec_driver tegra186_afc_codec = {
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.idle_bias_off = 1,
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.component_driver = {
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.dapm_widgets = tegra210_afc_widgets,
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.num_dapm_widgets = ARRAY_SIZE(tegra210_afc_widgets),
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.dapm_routes = tegra210_afc_routes,
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.num_dapm_routes = ARRAY_SIZE(tegra210_afc_routes),
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.controls = tegra186_afc_controls,
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.num_controls = ARRAY_SIZE(tegra186_afc_controls),
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},
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};
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static bool tegra210_afc_wr_rd_reg(struct device *dev, unsigned int reg)
|
|
{
|
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switch (reg) {
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case TEGRA210_AFC_AXBAR_RX_STATUS:
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case TEGRA210_AFC_AXBAR_RX_CIF_CTRL:
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case TEGRA210_AFC_AXBAR_RX_CYA:
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case TEGRA210_AFC_AXBAR_TX_STATUS:
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case TEGRA210_AFC_AXBAR_TX_INT_STATUS:
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case TEGRA210_AFC_AXBAR_TX_INT_MASK:
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case TEGRA210_AFC_AXBAR_TX_INT_SET:
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case TEGRA210_AFC_AXBAR_TX_INT_CLEAR:
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case TEGRA210_AFC_AXBAR_TX_CIF_CTRL:
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case TEGRA210_AFC_AXBAR_TX_CYA:
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case TEGRA210_AFC_ENABLE:
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case TEGRA210_AFC_SOFT_RESET:
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case TEGRA210_AFC_CG:
|
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case TEGRA210_AFC_STATUS:
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case TEGRA210_AFC_INT_STATUS:
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case TEGRA210_AFC_INT_MASK:
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case TEGRA210_AFC_INT_SET:
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case TEGRA210_AFC_INT_CLEAR:
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case TEGRA210_AFC_DEST_I2S_PARAMS:
|
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case TEGRA210_AFC_TXCIF_FIFO_PARAMS:
|
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case TEGRA210_AFC_CLK_PPM_DIFF:
|
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case TEGRA210_AFC_DBG_CTRL:
|
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case TEGRA210_AFC_TOTAL_SAMPLES:
|
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case TEGRA210_AFC_DECIMATION_SAMPLES:
|
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case TEGRA210_AFC_INTERPOLATION_SAMPLES:
|
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case TEGRA210_AFC_DBG_INTERNAL:
|
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case TEGRA210_AFC_LCOEF_1_4_0:
|
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case TEGRA210_AFC_LCOEF_1_4_1:
|
|
case TEGRA210_AFC_LCOEF_1_4_2:
|
|
case TEGRA210_AFC_LCOEF_1_4_3:
|
|
case TEGRA210_AFC_LCOEF_1_4_4:
|
|
case TEGRA210_AFC_LCOEF_1_4_5:
|
|
case TEGRA210_AFC_LCOEF_2_4_0:
|
|
case TEGRA210_AFC_LCOEF_2_4_1:
|
|
case TEGRA210_AFC_LCOEF_2_4_2:
|
|
case TEGRA210_AFC_CYA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
};
|
|
}
|
|
|
|
static bool tegra210_afc_volatile_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static const struct regmap_config tegra210_afc_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = TEGRA210_AFC_CYA,
|
|
.writeable_reg = tegra210_afc_wr_rd_reg,
|
|
.readable_reg = tegra210_afc_wr_rd_reg,
|
|
.volatile_reg = tegra210_afc_volatile_reg,
|
|
.reg_defaults = tegra210_afc_reg_defaults,
|
|
.num_reg_defaults = ARRAY_SIZE(tegra210_afc_reg_defaults),
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
static const struct tegra210_afc_soc_data soc_data_tegra210 = {
|
|
.afc_codec = &tegra210_afc_codec,
|
|
.num_i2s = 5,
|
|
.flag_module_select = false,
|
|
};
|
|
|
|
static const struct tegra210_afc_soc_data soc_data_tegra186 = {
|
|
.afc_codec = &tegra186_afc_codec,
|
|
.num_i2s = 6,
|
|
.flag_module_select = true,
|
|
};
|
|
|
|
static const struct of_device_id tegra210_afc_of_match[] = {
|
|
{ .compatible = "nvidia,tegra210-afc", .data = &soc_data_tegra210 },
|
|
{ .compatible = "nvidia,tegra186-afc", .data = &soc_data_tegra186 },
|
|
{},
|
|
};
|
|
|
|
static int tegra210_afc_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra210_afc *afc;
|
|
struct resource *mem;
|
|
void __iomem *regs;
|
|
int ret = 0;
|
|
const struct of_device_id *match;
|
|
struct tegra210_afc_soc_data *soc_data;
|
|
|
|
match = of_match_device(tegra210_afc_of_match, &pdev->dev);
|
|
if (!match) {
|
|
dev_err(&pdev->dev, "Error: No device match found\n");
|
|
return -ENODEV;
|
|
}
|
|
soc_data = (struct tegra210_afc_soc_data *)match->data;
|
|
|
|
afc = devm_kzalloc(&pdev->dev, sizeof(*afc), GFP_KERNEL);
|
|
if (!afc)
|
|
return -ENOMEM;
|
|
|
|
afc->soc_data = soc_data;
|
|
tegra210_afc_init(afc);
|
|
|
|
dev_set_drvdata(&pdev->dev, afc);
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
regs = devm_ioremap_resource(&pdev->dev, mem);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
afc->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
|
&tegra210_afc_regmap_config);
|
|
if (IS_ERR(afc->regmap)) {
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
|
return PTR_ERR(afc->regmap);
|
|
}
|
|
regcache_cache_only(afc->regmap, true);
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node,
|
|
"nvidia,ahub-afc-id",
|
|
&pdev->dev.id);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Missing property nvidia,ahub-afc-id\n");
|
|
return -ret;
|
|
}
|
|
|
|
/* Disable SLGC */
|
|
regmap_write(afc->regmap, TEGRA210_AFC_CG, 0);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
ret = snd_soc_register_codec(&pdev->dev, afc->soc_data->afc_codec,
|
|
tegra210_afc_dais,
|
|
ARRAY_SIZE(tegra210_afc_dais));
|
|
if (ret != 0) {
|
|
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
|
pm_runtime_disable(&pdev->dev);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra210_afc_platform_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra210_afc_runtime_suspend(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra210_afc_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra210_afc_runtime_suspend,
|
|
tegra210_afc_runtime_resume, NULL)
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra210_afc_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra210_afc_of_match,
|
|
.pm = &tegra210_afc_pm_ops,
|
|
},
|
|
.probe = tegra210_afc_platform_probe,
|
|
.remove = tegra210_afc_platform_remove,
|
|
};
|
|
module_platform_driver(tegra210_afc_driver)
|
|
|
|
MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra210 AFC ASoC driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra210_afc_of_match);
|