forked from rrcarlosr/Jetpack
500 lines
13 KiB
C
500 lines
13 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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/* minimum and maximum watchdog trigger timeout, in seconds */
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#define MIN_WDT_TIMEOUT 1
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#define MAX_WDT_TIMEOUT 255
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/* WDT registers */
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#define WDT_CFG 0x0
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#define WDT_CFG_PERIOD_SHIFT 4
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#define WDT_CFG_PERIOD_MASK 0xff
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#define WDT_CFG_INT_EN (1 << 12)
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#define WDT_CFG_FIQ_EN (1 << 13)
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#define WDT_CFG_PMC2CAR_RST_EN (1 << 15)
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#define WDT_STS 0x4
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#define WDT_STS_COUNT_SHIFT 4
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#define WDT_STS_COUNT_MASK 0xff
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#define WDT_STS_EXP_SHIFT 12
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#define WDT_STS_EXP_MASK 0x3
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#define WDT_CMD 0x8
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#define WDT_CMD_START_COUNTER (1 << 0)
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#define WDT_CMD_DISABLE_COUNTER (1 << 1)
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#define WDT_UNLOCK (0xc)
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#define WDT_UNLOCK_PATTERN (0xc45a << 0)
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/* Timer registers */
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#define TIMER_PTV 0x0
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#define TIMER_EN (1 << 31)
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#define TIMER_PERIODIC (1 << 30)
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/* Bit numbers for status flags */
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#define WDT_INIT_DAEMON_ACTIVE 0
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struct tegra_wdt {
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struct watchdog_device wdd;
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void __iomem *wdt_regs;
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void __iomem *tmr_regs;
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int irq;
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u8 timer_id;
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unsigned long status;
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bool enable_on_init;
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};
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static int tegra_wdt_ping(struct watchdog_device *wdd);
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/*
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* The total expiry count of Tegra WDTs is limited to HW design and depends
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* on skip configuration if supported. To be safe, we set the default expiry
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* count to 1. It should be updated later with value specified in device tree.
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*/
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static int expiry_count = 1;
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/*
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* Period value: Trigger Value is the time period and period value determines
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* number of periods for watchdog expiration i.e. effectively after time:
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* "period value" * "Trigger Vaue"
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*/
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#define WDT_TRG_PERIOD 1
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static int trigger_period = WDT_TRG_PERIOD;
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#define WDT_HEARTBEAT 120
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static int heartbeat = WDT_HEARTBEAT;
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module_param(heartbeat, int, 0);
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MODULE_PARM_DESC(heartbeat,
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"Watchdog heartbeats in seconds. (default = "
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__MODULE_STRING(WDT_HEARTBEAT) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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/*
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* Timer ID is required to be programmed to WDT_CFG register
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* As timer address and timer ID mapping is non-linear,
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* hence these function are defined to do the conversion.
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*/
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static resource_size_t tegra_tmr_addr(int timer_id, struct resource *tmr_res)
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{
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int i;
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resource_size_t tmr_addr;
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if (timer_id == 0)
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i = 10;
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else if (timer_id < 3)
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i = timer_id - 8;
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else if (timer_id > 9)
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i = timer_id + 1;
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else
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i = timer_id;
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tmr_addr = tmr_res->start - (10 - i) * resource_size(tmr_res);
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return tmr_addr;
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}
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static int tegra_tmr_index(struct resource *tmr_res)
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{
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int timer_id;
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/* Select Timer ID using Timer base address provided in DT:
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* [Base Addr:Timer#]
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* [0x00 : 1], [0x08 : 2], [0x50 : 3], [0x58 : 4], [0x60 : 5],
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* [0x68 : 6], [0x70 : 7], [0x78 : 8], [0x80 : 9], [0x88 : 0],
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* [0x90 : 10], [0x98 : 11], [0xA0 : 12], [0xA8 : 13]
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*/
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timer_id = ((3 + ((tmr_res->start & 0xff) - 0x50) / 8)) % 10;
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if ((tmr_res->start & 0xff) < 0x50)
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timer_id -= 4;
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if ((tmr_res->start & 0xff) > 0x88)
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timer_id += 9;
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return timer_id;
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}
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static irqreturn_t tegra_wdt_irq(int irq, void *data)
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{
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struct tegra_wdt *wdt = data;
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tegra_wdt_ping(&wdt->wdd);
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return IRQ_HANDLED;
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}
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static void tegra_wdt_ref(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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if (wdt->irq <= 0)
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return;
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/*
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* Remove the interrupt handler if userspace is taking over WDT.
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*/
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if (wdt->enable_on_init &&
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test_bit(WDT_INIT_DAEMON_ACTIVE, &wdt->status)) {
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printk("%s disable irq\n", __func__);
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disable_irq(wdt->irq);
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clear_bit(WDT_INIT_DAEMON_ACTIVE, &wdt->status);
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}
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}
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static int tegra_wdt_init(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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u32 val;
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/*
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* The timeout needs to be divided by expiry_count here so as to
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* keep the ultimate watchdog reset timeout the same as the program
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* timeout requested by application. The program timeout should make
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* sure WDT FIQ will never be asserted in a valid use case.
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*/
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val = (wdd->timeout * USEC_PER_SEC) / expiry_count;
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val |= (TIMER_EN | TIMER_PERIODIC);
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writel(val, wdt->tmr_regs + TIMER_PTV);
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/*
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* Set number of periods and start counter.
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*
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* Interrupt handler is not required for user space
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* WDT accesses, since the caller is responsible to ping the
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* WDT to reset the counter before expiration, through ioctls.
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*/
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val = (wdt->timer_id) |
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(trigger_period << WDT_CFG_PERIOD_SHIFT) |
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WDT_CFG_INT_EN | WDT_CFG_FIQ_EN | WDT_CFG_PMC2CAR_RST_EN;
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writel(val, wdt->wdt_regs + WDT_CFG);
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writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
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return 0;
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}
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/* Init, enable watchdog on WDT0 and create a thread to ping */
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static int tegra_wdt_daemon(struct watchdog_device *wdd)
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{
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struct platform_device *pdev = to_platform_device(wdd->parent);
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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int ret;
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if (!wdt->enable_on_init)
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return 0;
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wdt->irq = platform_get_irq(pdev, 0);
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if (wdt->irq <= 0) {
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dev_err(&pdev->dev, "failed to get WDT IRQ\n");
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return -ENXIO;
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}
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ret = devm_request_threaded_irq(&pdev->dev, wdt->irq, NULL,
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tegra_wdt_irq, IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
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dev_name(&pdev->dev), wdt);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to register irq %d err %d\n",
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wdt->irq, ret);
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return ret;
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}
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tegra_wdt_init(wdd);
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set_bit(WDT_INIT_DAEMON_ACTIVE, &wdt->status);
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dev_info(&pdev->dev, "Tegra WDT enabled on probe."
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" Timeout = %u seconds.\n", wdd->timeout);
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return 0;
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}
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static int tegra_wdt_start(struct watchdog_device *wdd)
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{
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tegra_wdt_init(wdd);
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tegra_wdt_ref(wdd);
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return 0;
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}
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static int tegra_wdt_stop(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK);
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writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD);
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writel(0, wdt->tmr_regs + TIMER_PTV);
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return 0;
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}
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static int tegra_wdt_ping(struct watchdog_device *wdd)
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{
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u32 val;
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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/* Disable timer */
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tegra_wdt_stop(wdd);
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/* Load the timeout value */
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val = (wdd->timeout * USEC_PER_SEC) / expiry_count;
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val |= (TIMER_EN | TIMER_PERIODIC);
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writel(val, wdt->tmr_regs + TIMER_PTV);
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/* Restart */
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writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
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return 0;
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}
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static int tegra_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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wdd->timeout = timeout;
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if (watchdog_active(wdd)) {
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tegra_wdt_stop(wdd);
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return tegra_wdt_init(wdd);
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}
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return 0;
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}
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static unsigned int tegra_wdt_get_timeleft(struct watchdog_device *wdd)
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{
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struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
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u32 val;
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int count;
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int exp;
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val = readl(wdt->wdt_regs + WDT_STS);
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/* Current countdown (from timeout) */
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count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK;
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/* Number of expirations */
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exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK;
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/*
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* The entire thing is divided by expiry_count because we are ticking
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* down expiry_count times faster due to needing to wait for the
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* expiry_count'th expiration.
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*/
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return (((3 - exp) * wdd->timeout) + count) / expiry_count;
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}
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static const struct watchdog_info tegra_wdt_info = {
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.options = WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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.firmware_version = 0,
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.identity = "Tegra Watchdog",
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};
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static struct watchdog_ops tegra_wdt_ops = {
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.owner = THIS_MODULE,
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.start = tegra_wdt_start,
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.stop = tegra_wdt_stop,
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.ping = tegra_wdt_ping,
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.set_timeout = tegra_wdt_set_timeout,
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.get_timeleft = tegra_wdt_get_timeleft,
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};
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static int tegra_wdt_probe(struct platform_device *pdev)
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{
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struct watchdog_device *wdd;
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struct tegra_wdt *wdt;
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struct resource *wdt_res, *tmr_res;
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struct device_node *np = pdev->dev.of_node;
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resource_size_t tmr_addr;
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u32 pval = 0;
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int ret = 0;
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wdt_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tmr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!wdt_res || !tmr_res) {
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dev_err(&pdev->dev, "incorrect wdt resources\n");
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return -ENOENT;
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}
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ret = of_property_read_u32(np, "nvidia,expiry-count", &pval);
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if (!ret)
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expiry_count = pval;
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ret = of_property_read_u32(np, "nvidia,heartbeat-init", &pval);
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if (!ret)
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heartbeat = pval;
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/*
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* Allocate our watchdog driver data, which has the
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* struct watchdog_device nested within it.
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*/
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->enable_on_init = of_property_read_bool(
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np, "nvidia,enable-on-init");
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/*
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* Get Timer index from (in decending priority):
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* from "nvidia,timer-index" DT property
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* from Timer Source Address in DT
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*/
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wdt->timer_id = tegra_tmr_index(tmr_res);
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ret = of_property_read_u32(np, "nvidia,timer-index", &pval);
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if (!ret) {
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/*
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* If timer-index is provided then either corresponding
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* timer source address or timer base address address
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* should be provided.
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*/
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if (wdt->timer_id && (wdt->timer_id != pval)) {
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dev_err(&pdev->dev, "Invalid Timer base address\n");
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return -EINVAL;
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}
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/* Skip adjust resource if timer source address is provided */
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if (!wdt->timer_id) {
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/* Timer timer address corresponding to timer ID */
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tmr_addr = tegra_tmr_addr(pval, tmr_res);
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ret = adjust_resource(tmr_res, tmr_addr,
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resource_size(tmr_res));
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if (ret < 0) {
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dev_err(&pdev->dev,
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"Failed to adjust resource:%d\n", ret);
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return ret;
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}
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}
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wdt->timer_id = pval;
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}
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wdt->wdt_regs = devm_ioremap_resource(&pdev->dev, wdt_res);
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if (IS_ERR(wdt->wdt_regs)) {
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dev_err(&pdev->dev, "failed ioremap wdt resource\n");
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return PTR_ERR(wdt->wdt_regs);
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}
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wdt->tmr_regs = devm_ioremap_resource(&pdev->dev, tmr_res);
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if (IS_ERR(wdt->tmr_regs)) {
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dev_err(&pdev->dev, "failed ioremap tmr resource\n");
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return PTR_ERR(wdt->tmr_regs);
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}
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/* Initialize struct watchdog_device. */
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wdd = &wdt->wdd;
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wdd->timeout = heartbeat;
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wdd->info = &tegra_wdt_info;
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wdd->ops = &tegra_wdt_ops;
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wdd->min_timeout = MIN_WDT_TIMEOUT * expiry_count;
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wdd->max_timeout = MAX_WDT_TIMEOUT * expiry_count;
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wdd->parent = &pdev->dev;
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watchdog_set_drvdata(wdd, wdt);
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watchdog_init_timeout(wdd, heartbeat, &pdev->dev);
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watchdog_set_nowayout(wdd, nowayout);
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/* Enable watchdog on WDT0 and create daemon to ping */
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ret = tegra_wdt_daemon(wdd);
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if (ret)
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return ret;
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ret = watchdog_register_device(wdd);
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if (ret) {
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dev_err(&pdev->dev,
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"failed to register watchdog device\n");
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return ret;
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}
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platform_set_drvdata(pdev, wdt);
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dev_info(&pdev->dev,
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"initialized (timeout = %d sec, nowayout = %d)\n",
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wdt->wdd.timeout, nowayout);
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return 0;
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}
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static int tegra_wdt_remove(struct platform_device *pdev)
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{
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struct tegra_wdt *wdt = platform_get_drvdata(pdev);
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tegra_wdt_stop(&wdt->wdd);
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if (wdt->irq > 0)
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devm_free_irq(&pdev->dev, wdt->irq, wdt);
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watchdog_unregister_device(&wdt->wdd);
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dev_info(&pdev->dev, "removed wdt\n");
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_wdt_runtime_suspend(struct device *dev)
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{
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struct tegra_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->wdd) ||
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test_bit(WDT_INIT_DAEMON_ACTIVE, &wdt->status))
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tegra_wdt_stop(&wdt->wdd);
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return 0;
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}
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static int tegra_wdt_runtime_resume(struct device *dev)
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{
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struct tegra_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->wdd) ||
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test_bit(WDT_INIT_DAEMON_ACTIVE, &wdt->status))
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tegra_wdt_init(&wdt->wdd);
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return 0;
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}
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#endif
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static const struct of_device_id tegra_wdt_of_match[] = {
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{ .compatible = "nvidia,tegra-wdt-t21x", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra_wdt_of_match);
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static const struct dev_pm_ops tegra_wdt_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(tegra_wdt_runtime_suspend,
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tegra_wdt_runtime_resume)
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};
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static struct platform_driver tegra_wdt_driver = {
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.probe = tegra_wdt_probe,
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.remove = tegra_wdt_remove,
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.driver = {
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.name = "tegra-wdt",
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.pm = &tegra_wdt_pm_ops,
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.of_match_table = tegra_wdt_of_match,
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},
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};
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module_platform_driver(tegra_wdt_driver);
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MODULE_AUTHOR("NVIDIA Corporation");
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MODULE_DESCRIPTION("Tegra Watchdog Driver");
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MODULE_LICENSE("GPL v2");
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