forked from rrcarlosr/Jetpack
780 lines
21 KiB
C
780 lines
21 KiB
C
/*
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* tegra_wdt_t18x.c: watchdog driver for NVIDIA tegra internal watchdog
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*
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* Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
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* Based on:
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* drivers/watchdog/softdog.c and
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* drivers/watchdog/omap_wdt.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/debugfs.h>
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#include <linux/fs.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/uaccess.h>
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#include <linux/watchdog.h>
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#include <soc/tegra/chip-id.h>
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#include <soc/tegra/pmc.h>
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/* The total expiry count of Tegra WDTs supported by HW */
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#define EXPIRY_COUNT 5
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/*
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* minimum and maximum Timer PTV in seconds
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* MAX_TMR_PTV defines maximum value in seconds which can be fed into
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* TOP_TKE_TMR_PTV which is of size 29 bits
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* MAX_TMR_PTV = (1 << 29) / USEC_PER_SEC;
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*/
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#define MIN_TMR_PTV 1
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#define MAX_TMR_PTV 536
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/*
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* To detect lockup condition, the heartbeat should be EXPIRY_COUNT*lockup.
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* It may be taken over later by timeout value requested by application.
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* Must be greater than MIN_TMR_PTV and lower than MAX_TMR_PTV*active_count.
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*/
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#define HEARTBEAT 120
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/* Watchdog configured to this time before reset during shutdown */
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#define SHUTDOWN_TIMEOUT 150
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/* Bit numbers for status flags */
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#define WDT_ENABLED 0
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#define WDT_ENABLED_ON_INIT 1
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#define WDT_ENABLED_USERSPACE 2
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struct tegra_wdt_t18x_soc {
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bool unmask_hw_irq;
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};
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struct tegra_wdt_t18x {
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struct device *dev;
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struct watchdog_device wdt;
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unsigned long users;
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void __iomem *wdt_source;
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void __iomem *wdt_timer;
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void __iomem *wdt_tke;
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struct dentry *root;
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const struct tegra_wdt_t18x_soc *soc;
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u32 config;
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int irq;
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int hwirq;
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unsigned long status;
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bool enable_on_init;
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int active_count;
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int shutdown_timeout;
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int wdt_index;
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int tmr_index;
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bool extended_suspend;
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bool config_locked;
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};
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/*
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* Global variable to store wdt pointer required by nvdumper and pmic to
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* change wdt state
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*/
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static struct tegra_wdt_t18x *t18x_wdt;
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close");
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static bool default_disable;
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module_param(default_disable, bool, 0644);
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MODULE_PARM_DESC(default_disable, "Default state of watchdog");
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static struct syscore_ops tegra_wdt_t18x_syscore_ops;
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static struct tegra_wdt_t18x *to_tegra_wdt_t18x(struct watchdog_device *wdt)
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{
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return container_of(wdt, struct tegra_wdt_t18x, wdt);
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}
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#define TOP_TKE_TKEIE_BASE 0x100
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#define TOP_TKE_TKEIE(i) (0x100 + 4 * (i))
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#define TOP_TKE_TKEIE_WDT_MASK(i) (1 << (16 + 4 * (i)))
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#define TOP_TKE_TMR_PTV 0
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#define TOP_TKE_TMR_EN BIT(31)
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#define TOP_TKE_TMR_PERIODIC BIT(30)
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#define TOP_TKE_TMR_PCR 0x4
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#define TOP_TKE_TMR_PCR_INTR BIT(30)
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#define WDT_CFG (0)
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#define WDT_CFG_PERIOD BIT(4)
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#define WDT_CFG_INT_EN BIT(12)
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#define WDT_CFG_FINT_EN BIT(13)
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#define WDT_CFG_REMOTE_INT_EN BIT(14)
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#define WDT_CFG_DBG_RST_EN BIT(15)
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#define WDT_CFG_SYS_PORST_EN BIT(16)
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#define WDT_CFG_ERR_THRESHOLD (7 << 20)
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#define WDT_STATUS (0x4)
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#define WDT_INTR_STAT BIT(1)
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#define WDT_CMD (0x8)
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#define WDT_CMD_START_COUNTER BIT(0)
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#define WDT_CMD_DISABLE_COUNTER BIT(1)
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#define WDT_UNLOCK (0xC)
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#define WDT_UNLOCK_PATTERN (0xC45A << 0)
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#define WDT_SKIP (0x10)
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#define WDT_SKIP_VAL(i, val) (((val) & 0x7) << (4 * (i)))
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#define TIMER_INDEX(add) ((((add) >> 16) & 0xF) - 0x2)
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#define WATCHDOG_INDEX(add) ((((add) >> 16) & 0xF) - 0xc)
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static int __tegra_wdt_t18x_ping(struct tegra_wdt_t18x *twdt_t18x)
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{
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u32 val;
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/* Disable timer, load the timeout value and restart. */
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writel(WDT_UNLOCK_PATTERN, twdt_t18x->wdt_source + WDT_UNLOCK);
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writel(WDT_CMD_DISABLE_COUNTER, twdt_t18x->wdt_source + WDT_CMD);
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writel(TOP_TKE_TMR_PCR_INTR, twdt_t18x->wdt_timer + TOP_TKE_TMR_PCR);
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val = (twdt_t18x->wdt.timeout * USEC_PER_SEC) / twdt_t18x->active_count;
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val |= (TOP_TKE_TMR_EN | TOP_TKE_TMR_PERIODIC);
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writel(val, twdt_t18x->wdt_timer + TOP_TKE_TMR_PTV);
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writel(WDT_CMD_START_COUNTER, twdt_t18x->wdt_source + WDT_CMD);
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dev_dbg(twdt_t18x->dev, "Watchdog%d: wdt cleared\n", twdt_t18x->wdt.id);
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return 0;
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}
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static irqreturn_t tegra_wdt_t18x_isr(int irq, void *data)
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{
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struct tegra_wdt_t18x *twdt_t18x = data;
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__tegra_wdt_t18x_ping(twdt_t18x);
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return IRQ_HANDLED;
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}
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static void tegra_wdt_t18x_ref(struct watchdog_device *wdt)
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{
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struct tegra_wdt_t18x *twdt_t18x = to_tegra_wdt_t18x(wdt);
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if (twdt_t18x->irq <= 0)
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return;
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/* Remove the interrupt handler if userspace is taking over WDT. */
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if (!test_and_set_bit(WDT_ENABLED_USERSPACE, &twdt_t18x->status) &&
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test_bit(WDT_ENABLED_ON_INIT, &twdt_t18x->status))
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disable_irq(twdt_t18x->irq);
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}
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static inline int tegra_wdt_t18x_skip(struct tegra_wdt_t18x *twdt_t18x)
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{
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u32 val = 0;
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int skip_count = 0;
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bool remote_skip = !(twdt_t18x->config & WDT_CFG_REMOTE_INT_EN);
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bool dbg_skip = !(twdt_t18x->config & WDT_CFG_DBG_RST_EN);
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if (remote_skip) {
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if (dbg_skip) {
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val |= WDT_SKIP_VAL(2, 2);
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skip_count += 2;
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} else {
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val |= WDT_SKIP_VAL(2, 1);
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skip_count += 1;
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}
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} else {
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if (dbg_skip) {
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val |= WDT_SKIP_VAL(3, 1);
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skip_count += 1;
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}
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}
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if (val)
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writel(val, twdt_t18x->wdt_source + WDT_SKIP);
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return skip_count;
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}
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static int __tegra_wdt_t18x_enable(struct tegra_wdt_t18x *twdt_t18x)
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{
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u32 val;
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/* Unmask IRQ. This has to be called after every WDT power gate */
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if (twdt_t18x->soc->unmask_hw_irq)
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writel(TOP_TKE_TKEIE_WDT_MASK(twdt_t18x->wdt_index),
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twdt_t18x->wdt_tke + TOP_TKE_TKEIE(twdt_t18x->hwirq));
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/* Update skip configuration and active expiry count */
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twdt_t18x->active_count = EXPIRY_COUNT - tegra_wdt_t18x_skip(twdt_t18x);
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if (twdt_t18x->active_count < 1)
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twdt_t18x->active_count = 1;
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writel(TOP_TKE_TMR_PCR_INTR, twdt_t18x->wdt_timer + TOP_TKE_TMR_PCR);
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/*
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* The timeout needs to be divided by active expiry count here so as
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* to keep the ultimate watchdog reset timeout the same as the program
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* timeout requested by application. The program timeout should make
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* sure WDT FIQ will never be asserted in a valid use case.
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*/
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val = (twdt_t18x->wdt.timeout * USEC_PER_SEC) / twdt_t18x->active_count;
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val |= (TOP_TKE_TMR_EN | TOP_TKE_TMR_PERIODIC);
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writel(val, twdt_t18x->wdt_timer + TOP_TKE_TMR_PTV);
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if (!twdt_t18x->config_locked)
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writel(twdt_t18x->config, twdt_t18x->wdt_source + WDT_CFG);
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writel(WDT_CMD_START_COUNTER, twdt_t18x->wdt_source + WDT_CMD);
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set_bit(WDT_ENABLED, &twdt_t18x->status);
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return 0;
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}
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static int __tegra_wdt_t18x_disable(struct tegra_wdt_t18x *twdt_t18x)
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{
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writel(WDT_UNLOCK_PATTERN, twdt_t18x->wdt_source + WDT_UNLOCK);
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writel(WDT_CMD_DISABLE_COUNTER, twdt_t18x->wdt_source + WDT_CMD);
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writel(0, twdt_t18x->wdt_timer + TOP_TKE_TMR_PTV);
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clear_bit(WDT_ENABLED, &twdt_t18x->status);
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return 0;
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}
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static int tegra_wdt_t18x_enable(struct watchdog_device *wdt)
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{
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struct tegra_wdt_t18x *twdt_t18x = to_tegra_wdt_t18x(wdt);
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return __tegra_wdt_t18x_enable(twdt_t18x);
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}
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static int tegra_wdt_t18x_disable(struct watchdog_device *wdt)
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{
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struct tegra_wdt_t18x *twdt_t18x = to_tegra_wdt_t18x(wdt);
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return __tegra_wdt_t18x_disable(twdt_t18x);
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}
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static int tegra_wdt_t18x_ping(struct watchdog_device *wdt)
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{
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struct tegra_wdt_t18x *twdt_t18x = to_tegra_wdt_t18x(wdt);
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tegra_wdt_t18x_ref(wdt);
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return __tegra_wdt_t18x_ping(twdt_t18x);
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}
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static int tegra_wdt_t18x_set_timeout(struct watchdog_device *wdt,
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unsigned int timeout)
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{
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struct tegra_wdt_t18x *twdt_t18x = to_tegra_wdt_t18x(wdt);
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tegra_wdt_t18x_disable(wdt);
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wdt->timeout = timeout;
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tegra_wdt_t18x_enable(wdt);
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dev_info(twdt_t18x->dev, "Watchdog(%d): wdt timeout set to %u sec\n",
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wdt->id, timeout);
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return 0;
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}
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static const struct watchdog_info tegra_wdt_t18x_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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.identity = "Tegra WDT",
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.firmware_version = 1,
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};
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static const struct watchdog_ops tegra_wdt_t18x_ops = {
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.owner = THIS_MODULE,
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.start = tegra_wdt_t18x_enable,
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.stop = tegra_wdt_t18x_disable,
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.ping = tegra_wdt_t18x_ping,
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.set_timeout = tegra_wdt_t18x_set_timeout,
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};
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#ifdef CONFIG_DEBUG_FS
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static int dump_registers_show(struct seq_file *s, void *unused)
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{
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struct tegra_wdt_t18x *twdt_t18x = s->private;
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seq_printf(s, "Timer config register \t\t0x%08x\n",
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readl(twdt_t18x->wdt_timer + TOP_TKE_TMR_PTV));
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seq_printf(s, "Timer status register \t\t0x%08x\n",
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readl(twdt_t18x->wdt_timer + TOP_TKE_TMR_PCR));
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seq_printf(s, "Watchdog config register \t0x%08x\n",
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readl(twdt_t18x->wdt_source + WDT_CFG));
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seq_printf(s, "Watchdog status register \t0x%08x\n",
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readl(twdt_t18x->wdt_source + WDT_STATUS));
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seq_printf(s, "Watchdog command register \t0x%08x\n",
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readl(twdt_t18x->wdt_source + WDT_CMD));
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seq_printf(s, "Watchdog skip register \t\t0x%08x\n",
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readl(twdt_t18x->wdt_source + WDT_SKIP));
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return 0;
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}
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static int disable_dbg_reset_show(struct seq_file *s, void *unused)
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{
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struct tegra_wdt_t18x *twdt_t18x = s->private;
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seq_printf(s, "%d\n",
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(twdt_t18x->config & WDT_CFG_DBG_RST_EN) ? 0 : 1);
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return 0;
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}
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static int disable_por_reset_show(struct seq_file *s, void *unused)
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{
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struct tegra_wdt_t18x *twdt_t18x = s->private;
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seq_printf(s, "%d\n",
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(twdt_t18x->config & WDT_CFG_SYS_PORST_EN) ? 0 : 1);
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return 0;
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}
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#define SIMPLE_FOPS(_name, _show) \
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static int dbg_open_##_name(struct inode *inode, struct file *file) \
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{ \
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return single_open(file, _show, inode->i_private); \
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} \
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static const struct file_operations _name##_fops = { \
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.open = dbg_open_##_name, \
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.read = seq_read, \
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.llseek = seq_lseek, \
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.release = single_release, \
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}
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SIMPLE_FOPS(dump_regs, dump_registers_show);
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SIMPLE_FOPS(disable_dbg_reset, disable_dbg_reset_show);
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SIMPLE_FOPS(disable_por_reset, disable_por_reset_show);
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static void tegra_wdt_t18x_debugfs_init(struct tegra_wdt_t18x *twdt_t18x)
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{
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struct dentry *root;
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struct dentry *retval;
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struct platform_device *pdev = to_platform_device(twdt_t18x->dev);
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root = debugfs_create_dir(pdev->name, NULL);
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if (IS_ERR_OR_NULL(root))
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goto clean;
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retval = debugfs_create_file("dump_regs", S_IRUGO | S_IWUSR,
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root, twdt_t18x, &dump_regs_fops);
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if (IS_ERR_OR_NULL(retval))
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goto clean;
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retval = debugfs_create_file("disable_dbg_reset", S_IRUGO | S_IWUSR,
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root, twdt_t18x,
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&disable_dbg_reset_fops);
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if (IS_ERR_OR_NULL(retval))
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goto clean;
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retval = debugfs_create_file("disable_por_reset", S_IRUGO | S_IWUSR,
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root, twdt_t18x,
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&disable_por_reset_fops);
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if (IS_ERR_OR_NULL(retval))
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goto clean;
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twdt_t18x->root = root;
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return;
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clean:
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dev_warn(twdt_t18x->dev, "Failed to create debugfs!\n");
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debugfs_remove_recursive(root);
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}
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#else /* !CONFIG_DEBUG_FS */
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static void tegra_wdt_t18x_debugfs_init(struct tegra_wdt_t18x *twdt_t18x)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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static int tegra_wdt_t18x_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res_wdt, *res_tmr, *res_tke;
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struct tegra_wdt_t18x *twdt_t18x;
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struct device_node *np = pdev->dev.of_node;
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struct of_phandle_args oirq;
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int timer_id, wdt_id;
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int skip_count = 0;
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u32 pval = 0;
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int ret;
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twdt_t18x = devm_kzalloc(&pdev->dev, sizeof(*twdt_t18x), GFP_KERNEL);
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if (!twdt_t18x)
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return -ENOMEM;
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ret = of_property_read_u32(np, "nvidia,shutdown-timeout", &pval);
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twdt_t18x->shutdown_timeout = (ret) ? SHUTDOWN_TIMEOUT : pval;
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twdt_t18x->soc = of_device_get_match_data(&pdev->dev);
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twdt_t18x->dev = &pdev->dev;
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twdt_t18x->wdt.info = &tegra_wdt_t18x_info;
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twdt_t18x->wdt.ops = &tegra_wdt_t18x_ops;
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ret = of_property_read_u32(np, "nvidia,expiry-count", &pval);
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if (!ret)
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dev_info(twdt_t18x->dev, "Expiry count is deprecated\n");
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watchdog_set_nowayout(&twdt_t18x->wdt, nowayout);
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twdt_t18x->irq = platform_get_irq(pdev, 0);
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if (twdt_t18x->irq < 0) {
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|
dev_err(&pdev->dev, "Interrupt is not available\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Find the IRQ number from the perspective of the interrupt
|
|
* controller. This is different than Linux's IRQ number
|
|
*/
|
|
ret = of_irq_parse_one(np, 0, &oirq);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to parse IRQ: %d\n", ret);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* The second entry is the IRQ */
|
|
twdt_t18x->hwirq = oirq.args[1];
|
|
|
|
twdt_t18x->enable_on_init = of_property_read_bool(np,
|
|
"nvidia,enable-on-init");
|
|
|
|
twdt_t18x->extended_suspend = of_property_read_bool(np,
|
|
"nvidia,extend-watchdog-suspend");
|
|
|
|
t18x_wdt = twdt_t18x;
|
|
platform_set_drvdata(pdev, twdt_t18x);
|
|
|
|
res_wdt = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
res_tmr = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
res_tke = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
|
if (!res_wdt || !res_tmr || !res_tke) {
|
|
dev_err(&pdev->dev, "Insufficient resources\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
/* WDT ID from base address */
|
|
wdt_id = WATCHDOG_INDEX(res_wdt->start);
|
|
ret = of_property_read_u32(np, "nvidia,watchdog-index", &pval);
|
|
if (!ret) {
|
|
twdt_t18x->wdt_index = pval;
|
|
|
|
/* If WDT index provided then address must be for base */
|
|
if (wdt_id && (wdt_id != twdt_t18x->wdt_index)) {
|
|
dev_err(dev, "WDT base address must be for WDT0\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Adjust address for WDT */
|
|
ret = adjust_resource(res_wdt, res_wdt->start + pval * 0x1000,
|
|
res_wdt->end - res_wdt->start);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Cannot adjust address of WDT: %d\n", ret);
|
|
return ret;
|
|
}
|
|
} else {
|
|
/* Watchdog index in list of wdts under top_tke */
|
|
twdt_t18x->wdt_index = wdt_id;
|
|
}
|
|
|
|
twdt_t18x->wdt_source = devm_ioremap_resource(&pdev->dev, res_wdt);
|
|
if (IS_ERR(twdt_t18x->wdt_source)) {
|
|
dev_err(&pdev->dev, "Cannot request memregion/iomap res_wdt\n");
|
|
return PTR_ERR(twdt_t18x->wdt_source);
|
|
}
|
|
|
|
twdt_t18x->config = readl(twdt_t18x->wdt_source + WDT_CFG);
|
|
twdt_t18x->config_locked = !!(twdt_t18x->config & WDT_CFG_INT_EN);
|
|
|
|
/*
|
|
* Get Timer index,
|
|
* First from BL, if locked else
|
|
* from DT property else
|
|
* From base address.
|
|
*/
|
|
if (twdt_t18x->config_locked) {
|
|
twdt_t18x->tmr_index = twdt_t18x->config & 0xF;
|
|
} else {
|
|
ret = of_property_read_u32(np, "nvidia,timer-index", &pval);
|
|
if (!ret)
|
|
twdt_t18x->tmr_index = pval;
|
|
else
|
|
twdt_t18x->tmr_index = TIMER_INDEX(res_tmr->start);
|
|
}
|
|
|
|
/*
|
|
* If timer ID from address different then timer index
|
|
* then adjust address.
|
|
*/
|
|
timer_id = TIMER_INDEX(res_tmr->start);
|
|
if (timer_id != twdt_t18x->tmr_index) {
|
|
if (timer_id) {
|
|
dev_err(dev, "Timer base address must be Timer0\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = adjust_resource(res_tmr, res_tmr->start +
|
|
twdt_t18x->tmr_index * 0x10000,
|
|
res_tmr->end - res_tmr->start);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Cannot adjust address of TMR:%d\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
twdt_t18x->wdt_timer = devm_ioremap_resource(&pdev->dev, res_tmr);
|
|
if (IS_ERR(twdt_t18x->wdt_timer)) {
|
|
dev_err(&pdev->dev, "Cannot request memregion/iomap res_tmr\n");
|
|
return PTR_ERR(twdt_t18x->wdt_timer);
|
|
}
|
|
|
|
twdt_t18x->wdt_tke = devm_ioremap_resource(&pdev->dev, res_tke);
|
|
if (IS_ERR(twdt_t18x->wdt_tke)) {
|
|
dev_err(&pdev->dev, "Cannot request memregion/iomap res_tke\n");
|
|
return PTR_ERR(twdt_t18x->wdt_tke);
|
|
}
|
|
|
|
if (!twdt_t18x->config_locked) {
|
|
/* Configure timer source and period */
|
|
twdt_t18x->config = twdt_t18x->tmr_index;
|
|
twdt_t18x->config |= WDT_CFG_PERIOD;
|
|
|
|
/* Enable local interrupt for WDT petting */
|
|
twdt_t18x->config |= WDT_CFG_INT_EN;
|
|
|
|
/*
|
|
* 'ErrorThreshold' field @ TKE_TOP_WDT1_WDTCR_0 decides the
|
|
* indication to HSM. The WDT logic asserts an error signal to
|
|
* HSM when ExpirationLevel >= ErrorThreshold. Retain the POR
|
|
* value to avoid nuisance trigger to HSM.
|
|
*/
|
|
twdt_t18x->config |= WDT_CFG_ERR_THRESHOLD;
|
|
|
|
/* Enable local FIQ and remote interrupt for debug dump */
|
|
twdt_t18x->config |= WDT_CFG_FINT_EN;
|
|
|
|
if (!of_property_read_bool(np,
|
|
"nvidia,disable-remote-interrupt"))
|
|
twdt_t18x->config |= WDT_CFG_REMOTE_INT_EN;
|
|
else
|
|
skip_count++;
|
|
|
|
/*
|
|
* Debug and POR reset events should be enabled by default.
|
|
* Disable only if explicitly indicated in device tree or
|
|
* HALT_IN_FIQ is set, so as to allow external debugger to poke.
|
|
*/
|
|
if (!tegra_pmc_is_halt_in_fiq()) {
|
|
if (!of_property_read_bool(
|
|
np, "nvidia,disable-debug-reset"))
|
|
twdt_t18x->config |= WDT_CFG_DBG_RST_EN;
|
|
else
|
|
skip_count++;
|
|
|
|
if (!of_property_read_bool(
|
|
np, "nvidia,disable-por-reset"))
|
|
twdt_t18x->config |= WDT_CFG_SYS_PORST_EN;
|
|
}
|
|
}
|
|
|
|
twdt_t18x->wdt.min_timeout = MIN_TMR_PTV;
|
|
twdt_t18x->wdt.max_timeout = MAX_TMR_PTV * (EXPIRY_COUNT - skip_count);
|
|
ret = watchdog_init_timeout(&twdt_t18x->wdt, 0, &pdev->dev);
|
|
if (ret < 0)
|
|
twdt_t18x->wdt.timeout = HEARTBEAT;
|
|
|
|
tegra_wdt_t18x_disable(&twdt_t18x->wdt);
|
|
writel(TOP_TKE_TMR_PCR_INTR, twdt_t18x->wdt_timer + TOP_TKE_TMR_PCR);
|
|
|
|
ret = devm_request_threaded_irq(&pdev->dev, twdt_t18x->irq,
|
|
NULL, tegra_wdt_t18x_isr,
|
|
IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
|
|
dev_name(&pdev->dev), twdt_t18x);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to register irq %d err %d\n",
|
|
twdt_t18x->irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
if (twdt_t18x->enable_on_init) {
|
|
tegra_wdt_t18x_enable(&twdt_t18x->wdt);
|
|
set_bit(WDOG_ACTIVE, &twdt_t18x->wdt.status);
|
|
set_bit(WDT_ENABLED_ON_INIT, &twdt_t18x->status);
|
|
dev_info(twdt_t18x->dev, "Tegra WDT init timeout = %u sec\n",
|
|
twdt_t18x->wdt.timeout);
|
|
}
|
|
|
|
tegra_wdt_t18x_debugfs_init(twdt_t18x);
|
|
|
|
if (twdt_t18x->extended_suspend)
|
|
register_syscore_ops(&tegra_wdt_t18x_syscore_ops);
|
|
|
|
ret = devm_watchdog_register_device(&pdev->dev, &twdt_t18x->wdt);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register watchdog device\n");
|
|
goto cleanup;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Registered successfully\n");
|
|
|
|
return 0;
|
|
|
|
cleanup:
|
|
__tegra_wdt_t18x_disable(twdt_t18x);
|
|
|
|
if (twdt_t18x->extended_suspend)
|
|
unregister_syscore_ops(&tegra_wdt_t18x_syscore_ops);
|
|
|
|
debugfs_remove_recursive(twdt_t18x->root);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void tegra_wdt_t18x_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct tegra_wdt_t18x *twdt_t18x = platform_get_drvdata(pdev);
|
|
|
|
if (twdt_t18x->shutdown_timeout) {
|
|
twdt_t18x->wdt.timeout = twdt_t18x->shutdown_timeout;
|
|
__tegra_wdt_t18x_ping(twdt_t18x);
|
|
return;
|
|
}
|
|
|
|
__tegra_wdt_t18x_disable(twdt_t18x);
|
|
}
|
|
|
|
static int tegra_wdt_t18x_remove(struct platform_device *pdev)
|
|
{
|
|
struct tegra_wdt_t18x *twdt_t18x = platform_get_drvdata(pdev);
|
|
|
|
t18x_wdt = NULL;
|
|
__tegra_wdt_t18x_disable(twdt_t18x);
|
|
|
|
if (twdt_t18x->extended_suspend)
|
|
unregister_syscore_ops(&tegra_wdt_t18x_syscore_ops);
|
|
|
|
debugfs_remove_recursive(twdt_t18x->root);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int tegra_wdt_t18x_suspend(struct device *dev)
|
|
{
|
|
struct tegra_wdt_t18x *twdt_t18x = dev_get_drvdata(dev);
|
|
|
|
if (twdt_t18x->extended_suspend)
|
|
__tegra_wdt_t18x_ping(twdt_t18x);
|
|
else
|
|
__tegra_wdt_t18x_disable(twdt_t18x);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_wdt_t18x_resume(struct device *dev)
|
|
{
|
|
struct tegra_wdt_t18x *twdt_t18x = dev_get_drvdata(dev);
|
|
|
|
if (watchdog_active(&twdt_t18x->wdt)) {
|
|
if (twdt_t18x->extended_suspend)
|
|
__tegra_wdt_t18x_ping(twdt_t18x);
|
|
else
|
|
__tegra_wdt_t18x_enable(twdt_t18x);
|
|
} else {
|
|
if (twdt_t18x->extended_suspend)
|
|
__tegra_wdt_t18x_disable(twdt_t18x);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_wdt_t18x_syscore_suspend(void)
|
|
{
|
|
if (t18x_wdt && t18x_wdt->extended_suspend)
|
|
__tegra_wdt_t18x_disable(t18x_wdt);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_wdt_t18x_syscore_resume(void)
|
|
{
|
|
if (t18x_wdt && t18x_wdt->extended_suspend)
|
|
__tegra_wdt_t18x_enable(t18x_wdt);
|
|
}
|
|
#else
|
|
static int tegra_wdt_t18x_syscore_suspend(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void tegra_wdt_t18x_syscore_resume(void) { }
|
|
#endif
|
|
|
|
static struct syscore_ops tegra_wdt_t18x_syscore_ops = {
|
|
.suspend = tegra_wdt_t18x_syscore_suspend,
|
|
.resume = tegra_wdt_t18x_syscore_resume,
|
|
};
|
|
|
|
static const struct dev_pm_ops tegra_wdt_t18x_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_wdt_t18x_suspend, tegra_wdt_t18x_resume)
|
|
};
|
|
|
|
static const struct tegra_wdt_t18x_soc t18x_wdt_silicon = {
|
|
.unmask_hw_irq = true,
|
|
};
|
|
|
|
static const struct tegra_wdt_t18x_soc t18x_wdt_sim = {
|
|
.unmask_hw_irq = false,
|
|
};
|
|
|
|
static const struct of_device_id tegra_wdt_t18x_match[] = {
|
|
{ .compatible = "nvidia,tegra-wdt-t19x", .data = &t18x_wdt_silicon},
|
|
{ .compatible = "nvidia,tegra-wdt-t18x", .data = &t18x_wdt_silicon},
|
|
{ .compatible = "nvidia,tegra-wdt-t18x-linsim", .data = &t18x_wdt_sim},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra_wdt_t18x_match);
|
|
|
|
static struct platform_driver tegra_wdt_t18x_driver = {
|
|
.probe = tegra_wdt_t18x_probe,
|
|
.remove = tegra_wdt_t18x_remove,
|
|
.shutdown = tegra_wdt_t18x_shutdown,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "tegra_wdt_t18x",
|
|
.pm = &tegra_wdt_t18x_pm_ops,
|
|
.of_match_table = of_match_ptr(tegra_wdt_t18x_match),
|
|
},
|
|
};
|
|
|
|
static int __init tegra_wdt_t18x_init(void)
|
|
{
|
|
return platform_driver_register(&tegra_wdt_t18x_driver);
|
|
}
|
|
|
|
static void __exit tegra_wdt_t18x_exit(void)
|
|
{
|
|
platform_driver_unregister(&tegra_wdt_t18x_driver);
|
|
}
|
|
|
|
subsys_initcall(tegra_wdt_t18x_init);
|
|
module_exit(tegra_wdt_t18x_exit);
|
|
|
|
MODULE_AUTHOR("NVIDIA Corporation");
|
|
MODULE_DESCRIPTION("Tegra Watchdog Driver");
|
|
MODULE_LICENSE("GPL v2");
|