forked from rrcarlosr/Jetpack
75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
/*
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* qspi-tegra.h: SPI interface for Nvidia Tegra210 QSPI controller.
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*
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* Copyright (C) 2011-2018 NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef _LINUX_QSPI_TEGRA_H
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#define _LINUX_QSPI_TEGRA_H
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struct tegra_qspi_platform_data {
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int dma_req_sel;
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u32 qspi_max_frequency;
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bool is_clkon_always;
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};
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/*
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* Controller data from device to pass some info like
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* bus width, mode, tap delay etc.
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*/
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struct tegra_qspi_device_controller_data {
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bool is_hw_based_cs;
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int cs_setup_clk_count;
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int cs_hold_clk_count;
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int rx_clk_tap_delay;
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int tx_clk_tap_delay;
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bool rx_tap_delay;
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bool tx_tap_delay;
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u32 x1_len_limit;
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u32 x1_bus_speed;
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u32 x1_dymmy_cycle;
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u32 x4_bus_speed;
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u32 x4_dymmy_cycle;
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bool x4_is_ddr;
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bool ifddr_div2_sdr;
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bool is_combined_seq_mode_en;
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u8 bus_clk_div;
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};
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enum qspi_bus_width {
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X1,
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X2,
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X4,
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};
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/* Bits 11,10,9,8 for op mode */
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#define get_op_mode(x) (((x) >> 8) & 0xF)
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#define set_op_mode(x) (((x) & 0xF) << 8)
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/* Use bit 13,12 for x1/x2/x4 */
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#define get_bus_width(x) (((x) >> 12) & 0x3)
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#define set_bus_width(x) (((x) & 0x3) << 12)
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/* Set bit 14 for ddr */
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#define get_sdr_ddr(x) (((x) >> 14) & 0x1)
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#define set_sdr_ddr (1 << 14)
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#define get_dummy_cyl(x) ((x) & 0xff)
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#define set_dummy_cyl(x) ((x) & 0xff)
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#endif /* _LINUX_QSPI_TEGRA_H */
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