forked from rrcarlosr/Jetpack
45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Definitions for Jetson tegra210-p3448-0000-p3449-0000-a02 board.
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*
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* Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#define JETSON_COMPATIBLE "nvidia,p3449-0000-b00+p3448-0000-b00", "nvidia,p3449-0000-a02+p3448-0000-a02"
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/* SoC function name for clock signal on 40-pin header pin 7 */
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#define HDR40_CLK "aud"
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/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
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#define HDR40_I2S "i2s4b"
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/* SoC function name for PWM interface on 40-pin header pin 32 */
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#define HDR40_PWM0 "pwm0"
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/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, 24 and 26 */
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#define HDR40_SPI "spi1"
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/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
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#define HDR40_UART "uartb"
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/* SoC pin name definitions for 40-pin header */
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#define HDR40_PIN7 "aud_mclk_pbb0"
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#define HDR40_PIN11 "uart2_rts_pg2"
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#define HDR40_PIN12 "dap4_sclk_pj7"
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#define HDR40_PIN13 "spi2_sck_pb6"
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#define HDR40_PIN15 "lcd_te_py2"
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#define HDR40_PIN16 "spi2_cs1_pdd0"
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#define HDR40_PIN18 "spi2_cs0_pb7"
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#define HDR40_PIN19 "spi1_mosi_pc0"
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#define HDR40_PIN21 "spi1_miso_pc1"
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#define HDR40_PIN22 "spi2_miso_pb5"
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#define HDR40_PIN23 "spi1_sck_pc2"
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#define HDR40_PIN24 "spi1_cs0_pc3"
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#define HDR40_PIN26 "spi1_cs1_pc4"
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#define HDR40_PIN29 "cam_af_en_ps5"
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#define HDR40_PIN31 "pz0"
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#define HDR40_PIN32 "lcd_bl_pwm_pv0"
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#define HDR40_PIN33 "pe6"
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#define HDR40_PIN35 "dap4_fs_pj4"
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#define HDR40_PIN36 "uart2_cts_pg3"
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#define HDR40_PIN37 "spi2_mosi_pb4"
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#define HDR40_PIN38 "dap4_din_pj5"
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#define HDR40_PIN40 "dap4_dout_pj6"
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