forked from rrcarlosr/Jetpack
188 lines
6.8 KiB
C
188 lines
6.8 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef BPMP_ABI_MACH_T194_RESET_H
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#define BPMP_ABI_MACH_T194_RESET_H
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/**
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* @file
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* @defgroup bpmp_reset_ids Reset ID's
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* @brief Identifiers for Resets controllable by firmware
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* @{
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*/
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#define TEGRA194_RESET_ACTMON 1U
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#define TEGRA194_RESET_ADSP_ALL 2U
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#define TEGRA194_RESET_AFI 3U
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#define TEGRA194_RESET_CAN1 4U
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#define TEGRA194_RESET_CAN2 5U
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#define TEGRA194_RESET_DLA0 6U
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#define TEGRA194_RESET_DLA1 7U
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#define TEGRA194_RESET_DPAUX 8U
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#define TEGRA194_RESET_DPAUX1 9U
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#define TEGRA194_RESET_DPAUX2 10U
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#define TEGRA194_RESET_DPAUX3 11U
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#define TEGRA194_RESET_EQOS 17U
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#define TEGRA194_RESET_GPCDMA 18U
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#define TEGRA194_RESET_GPU 19U
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#define TEGRA194_RESET_HDA 20U
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#define TEGRA194_RESET_HDA2CODEC_2X 21U
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#define TEGRA194_RESET_HDA2HDMICODEC 22U
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#define TEGRA194_RESET_HOST1X 23U
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#define TEGRA194_RESET_I2C1 24U
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#define TEGRA194_RESET_I2C10 25U
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#define TEGRA194_RESET_RSVD_26 26U
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#define TEGRA194_RESET_RSVD_27 27U
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#define TEGRA194_RESET_RSVD_28 28U
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#define TEGRA194_RESET_I2C2 29U
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#define TEGRA194_RESET_I2C3 30U
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#define TEGRA194_RESET_I2C4 31U
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#define TEGRA194_RESET_I2C6 32U
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#define TEGRA194_RESET_I2C7 33U
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#define TEGRA194_RESET_I2C8 34U
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#define TEGRA194_RESET_I2C9 35U
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#define TEGRA194_RESET_ISP 36U
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#define TEGRA194_RESET_MIPI_CAL 37U
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#define TEGRA194_RESET_MPHY_CLK_CTL 38U
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#define TEGRA194_RESET_MPHY_L0_RX 39U
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#define TEGRA194_RESET_MPHY_L0_TX 40U
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#define TEGRA194_RESET_MPHY_L1_RX 41U
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#define TEGRA194_RESET_MPHY_L1_TX 42U
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#define TEGRA194_RESET_NVCSI 43U
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#define TEGRA194_RESET_NVDEC 44U
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#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45U
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#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46U
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#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47U
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#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48U
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#define TEGRA194_RESET_NVDISPLAY0_MISC 49U
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#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50U
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#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51U
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#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52U
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#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53U
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#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54U
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#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55U
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#define TEGRA194_RESET_RSVD_56 56U
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#define TEGRA194_RESET_RSVD_57 57U
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#define TEGRA194_RESET_RSVD_58 58U
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#define TEGRA194_RESET_NVENC 59U
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#define TEGRA194_RESET_NVENC1 60U
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#define TEGRA194_RESET_NVJPG 61U
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#define TEGRA194_RESET_PCIE 62U
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#define TEGRA194_RESET_PCIEXCLK 63U
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#define TEGRA194_RESET_RSVD_64 64U
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#define TEGRA194_RESET_RSVD_65 65U
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#define TEGRA194_RESET_PVA0_ALL 66U
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#define TEGRA194_RESET_PVA1_ALL 67U
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#define TEGRA194_RESET_PWM1 68U
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#define TEGRA194_RESET_PWM2 69U
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#define TEGRA194_RESET_PWM3 70U
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#define TEGRA194_RESET_PWM4 71U
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#define TEGRA194_RESET_PWM5 72U
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#define TEGRA194_RESET_PWM6 73U
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#define TEGRA194_RESET_PWM7 74U
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#define TEGRA194_RESET_PWM8 75U
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#define TEGRA194_RESET_QSPI0 76U
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#define TEGRA194_RESET_QSPI1 77U
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#define TEGRA194_RESET_SATA 78U
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#define TEGRA194_RESET_SATACOLD 79U
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#define TEGRA194_RESET_SCE_ALL 80U
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#define TEGRA194_RESET_RCE_ALL 81U
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#define TEGRA194_RESET_SDMMC1 82U
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#define TEGRA194_RESET_RSVD_83 83U
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#define TEGRA194_RESET_SDMMC3 84U
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#define TEGRA194_RESET_SDMMC4 85U
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#define TEGRA194_RESET_SE 86U
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#define TEGRA194_RESET_SOR0 87U
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#define TEGRA194_RESET_SOR1 88U
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#define TEGRA194_RESET_SOR2 89U
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#define TEGRA194_RESET_SOR3 90U
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#define TEGRA194_RESET_SPI1 91U
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#define TEGRA194_RESET_SPI2 92U
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#define TEGRA194_RESET_SPI3 93U
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#define TEGRA194_RESET_SPI4 94U
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#define TEGRA194_RESET_TACH 95U
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#define TEGRA194_RESET_RSVD_96 96U
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#define TEGRA194_RESET_TSCTNVI 97U
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#define TEGRA194_RESET_TSEC 98U
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#define TEGRA194_RESET_TSECB 99U
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#define TEGRA194_RESET_UARTA 100U
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#define TEGRA194_RESET_UARTB 101U
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#define TEGRA194_RESET_UARTC 102U
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#define TEGRA194_RESET_UARTD 103U
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#define TEGRA194_RESET_UARTE 104U
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#define TEGRA194_RESET_UARTF 105U
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#define TEGRA194_RESET_UARTG 106U
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#define TEGRA194_RESET_UARTH 107U
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#define TEGRA194_RESET_UFSHC 108U
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#define TEGRA194_RESET_UFSHC_AXI_M 109U
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#define TEGRA194_RESET_UFSHC_LP_SEQ 110U
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#define TEGRA194_RESET_RSVD_111 111U
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#define TEGRA194_RESET_VI 112U
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#define TEGRA194_RESET_VIC 113U
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#define TEGRA194_RESET_XUSB_PADCTL 114U
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#define TEGRA194_RESET_NVDEC1 115U
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#define TEGRA194_RESET_PEX0_CORE_0 116U
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#define TEGRA194_RESET_PEX0_CORE_1 117U
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#define TEGRA194_RESET_PEX0_CORE_2 118U
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#define TEGRA194_RESET_PEX0_CORE_3 119U
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#define TEGRA194_RESET_PEX0_CORE_4 120U
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#define TEGRA194_RESET_PEX0_CORE_0_APB 121U
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#define TEGRA194_RESET_PEX0_CORE_1_APB 122U
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#define TEGRA194_RESET_PEX0_CORE_2_APB 123U
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#define TEGRA194_RESET_PEX0_CORE_3_APB 124U
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#define TEGRA194_RESET_PEX0_CORE_4_APB 125U
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#define TEGRA194_RESET_PEX0_COMMON_APB 126U
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#define TEGRA194_RESET_SLVSEC 127U
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#define TEGRA194_RESET_NVLINK 128U
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#define TEGRA194_RESET_PEX1_CORE_5 129U
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#define TEGRA194_RESET_PEX1_CORE_5_APB 130U
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#define TEGRA194_RESET_CVNAS 131U
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#define TEGRA194_RESET_CVNAS_FCM 132U
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#define TEGRA194_RESET_NVHS_UPHY 133U
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#define TEGRA194_RESET_NVHS_UPHY_PLL0 134U
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#define TEGRA194_RESET_NVHS_UPHY_L0 135U
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#define TEGRA194_RESET_NVHS_UPHY_L1 136U
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#define TEGRA194_RESET_NVHS_UPHY_L2 137U
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#define TEGRA194_RESET_NVHS_UPHY_L3 138U
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#define TEGRA194_RESET_NVHS_UPHY_L4 139U
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#define TEGRA194_RESET_NVHS_UPHY_L5 140U
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#define TEGRA194_RESET_NVHS_UPHY_L6 141U
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#define TEGRA194_RESET_NVHS_UPHY_L7 142U
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#define TEGRA194_RESET_NVHS_UPHY_PM 143U
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#define TEGRA194_RESET_DMIC5 144U
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#define TEGRA194_RESET_APE 145U
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#define TEGRA194_RESET_PEX_USB_UPHY 146U
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#define TEGRA194_RESET_PEX_USB_UPHY_L0 147U
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#define TEGRA194_RESET_PEX_USB_UPHY_L1 148U
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#define TEGRA194_RESET_PEX_USB_UPHY_L2 149U
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#define TEGRA194_RESET_PEX_USB_UPHY_L3 150U
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#define TEGRA194_RESET_PEX_USB_UPHY_L4 151U
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#define TEGRA194_RESET_PEX_USB_UPHY_L5 152U
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#define TEGRA194_RESET_PEX_USB_UPHY_L6 153U
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#define TEGRA194_RESET_PEX_USB_UPHY_L7 154U
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#define TEGRA194_RESET_PEX_USB_UPHY_L8 155U
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#define TEGRA194_RESET_PEX_USB_UPHY_L9 156U
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#define TEGRA194_RESET_PEX_USB_UPHY_L10 157U
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#define TEGRA194_RESET_PEX_USB_UPHY_L11 158U
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159U
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160U
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161U
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#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162U
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#define TEGRA194_RESET_MSSNVL 180U
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/** @} */
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#endif
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