forked from rrcarlosr/Jetpack
60 lines
2.1 KiB
C
60 lines
2.1 KiB
C
#ifndef _DT_BINDINGS_MEMORY_TEGRA194_SWGROUP_H
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#define _DT_BINDINGS_MEMORY_TEGRA194_SWGROUP_H
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/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* This is the t19x specific component of the new SID dt-binding.
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*/
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#define TEGRA_SID_RCE 0x2a /* 42 */
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#define TEGRA_SID_RCE_VM2 0x2b /* 43 */
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#define TEGRA_SID_RCE_RM 0x2F /* 47 */
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#define TEGRA_SID_VIFALC 0x30 /* 48 */
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#define TEGRA_SID_ISPFALC 0x31 /* 49 */
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#define TEGRA_SID_MIU 0x50 /* 80 */
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#define TEGRA_SID_NVDLA0 0x51 /* 81 */
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#define TEGRA_SID_NVDLA1 0x52 /* 82 */
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#define TEGRA_SID_PVA0 0x53 /* 83 */
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#define TEGRA_SID_PVA1 0x54 /* 84 */
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#define TEGRA_SID_NVENC1 0x55 /* 85 */
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#define TEGRA_SID_PCIE0 0x56 /* 86 */
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#define TEGRA_SID_PCIE1 0x57 /* 87 */
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#define TEGRA_SID_PCIE2 0x58 /* 88 */
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#define TEGRA_SID_PCIE3 0x59 /* 89 */
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#define TEGRA_SID_PCIE4 0x5A /* 90 */
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#define TEGRA_SID_PCIE5 0x5B /* 91 */
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#define TEGRA_SID_NVDEC1 0x5C /* 92 */
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#define TEGRA_SID_RCE_VM3 0x61 /* 97 */
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#define TEGRA_SID_VI_VM2 0x62 /* 98 */
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#define TEGRA_SID_VI_VM3 0x63 /* 99 */
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#endif
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