forked from rrcarlosr/Jetpack
135 lines
4.0 KiB
Plaintext
135 lines
4.0 KiB
Plaintext
/*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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/ {
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aliases {
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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spi6 = &qspi0;
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spi7 = &qspi1;
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};
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spi0: spi@3210000 {
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compatible = "nvidia,tegra186-spi";
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reg = <0x0 0x03210000 0x0 0x10000>;
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interrupts = <0 36 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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dmas = <&gpcdma 15>, <&gpcdma 15>;
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dma-names = "rx", "tx";
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spi-max-frequency = <65000000>;
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nvidia,clk-parents = "pll_p", "clk_m";
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clocks = <&bpmp_clks TEGRA194_CLK_SPI1>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
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<&bpmp_clks TEGRA194_CLK_CLK_M>;
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clock-names = "spi", "pll_p", "clk_m";
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resets = <&bpmp_resets TEGRA194_RESET_SPI1>;
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reset-names = "spi";
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status = "disabled";
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};
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spi1: spi@c260000 {
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compatible = "nvidia,tegra186-spi";
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reg = <0x0 0x0c260000 0x0 0x10000>;
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interrupts = <0 37 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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dmas = <&gpcdma 16>, <&gpcdma 16>;
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dma-names = "rx", "tx";
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spi-max-frequency = <65000000>;
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nvidia,clk-parents = "pll_p", "osc";
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clocks = <&bpmp_clks TEGRA194_CLK_SPI2>,
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<&bpmp_clks TEGRA194_CLK_PLLAON>,
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<&bpmp_clks TEGRA194_CLK_OSC>;
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clock-names = "spi", "pll_p", "osc";
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resets = <&bpmp_resets TEGRA194_RESET_SPI2>;
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reset-names = "spi";
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status = "disabled";
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};
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spi2: spi@3230000 {
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compatible = "nvidia,tegra186-spi";
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reg = <0x0 0x03230000 0x0 0x10000>;
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interrupts = <0 38 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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dmas = <&gpcdma 17>, <&gpcdma 17>;
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dma-names = "rx", "tx";
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spi-max-frequency = <65000000>;
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nvidia,clk-parents = "pll_p", "clk_m";
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clocks = <&bpmp_clks TEGRA194_CLK_SPI3>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
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<&bpmp_clks TEGRA194_CLK_CLK_M>;
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clock-names = "spi", "pll_p", "clk_m";
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resets = <&bpmp_resets TEGRA194_RESET_SPI3>;
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reset-names = "spi";
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status = "disabled";
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};
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qspi0: spi@3270000 {
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compatible = "nvidia,tegra186-qspi";
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reg = <0x0 0x3270000 0x0 0x10000>;
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interrupts = < 0 35 0x04 >;
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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dmas = <&gpcdma 5>, <&gpcdma 5>;
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dma-names = "rx", "tx";
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spi-max-frequency = <204000000>;
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nvidia,clk-parents = "pllc", "pll_p";
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clocks = <&bpmp_clks TEGRA194_CLK_QSPI0>,
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<&bpmp_clks TEGRA194_CLK_QSPI0_PM>,
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<&bpmp_clks TEGRA194_CLK_PLLC>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "qspi", "qspi_out", "pllc", "pll_p";
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resets = <&bpmp_resets TEGRA194_RESET_QSPI0>;
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reset-names = "qspi";
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status = "disabled";
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};
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qspi1: spi@3300000 {
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compatible = "nvidia,tegra186-qspi";
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reg = <0x0 0x3300000 0x0 0x10000>;
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interrupts = < 0 39 0x04 >;
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#address-cells = <1>;
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#size-cells = <0>;
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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dma-coherent;
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dmas = <&gpcdma 6>, <&gpcdma 6>;
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dma-names = "rx", "tx";
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spi-max-frequency = <204000000>;
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nvidia,clk-parents = "pllc", "pll_p";
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clocks = <&bpmp_clks TEGRA194_CLK_QSPI1>,
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<&bpmp_clks TEGRA194_CLK_QSPI1_PM>,
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<&bpmp_clks TEGRA194_CLK_PLLC>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "qspi", "qspi_out", "pllc", "pll_p";
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resets = <&bpmp_resets TEGRA194_RESET_QSPI1>;
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reset-names = "qspi";
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status = "disabled";
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};
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};
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