forked from rrcarlosr/Jetpack
120 lines
1.7 KiB
Plaintext
120 lines
1.7 KiB
Plaintext
/*
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* tegra194-soc-sim.dtsi: Simulation and Emulation SOC base
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* DTSI file used for all sim DTSI.
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <tegra194-soc/tegra194-soc-base.dtsi>
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/ {
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reserved-memory {
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grid-of-semaphores {
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status = "okay";
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};
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};
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tegra-carveouts {
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status = "okay";
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};
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tegra-cvnas {
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status = "okay";
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};
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power-domain {
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status = "okay";
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};
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interrupt-controller {
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status = "okay";
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};
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mc {
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status = "okay";
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};
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mc_sid@2c00000 {
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status = "okay";
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};
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iommu@12000000 {
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status = "okay";
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};
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tegra-hsp@c150000 {
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status = "okay";
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};
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tegra-hsp@3c00000 {
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status = "okay";
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};
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host1x {
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ctx0 {
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status = "okay";
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};
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ctx1 {
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status = "okay";
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};
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ctx2 {
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status = "okay";
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};
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ctx3 {
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status = "okay";
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};
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ctx4 {
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status = "okay";
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};
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ctx5 {
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status = "okay";
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};
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ctx6 {
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status = "okay";
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};
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ctx7 {
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status = "okay";
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};
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};
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psci {
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status = "okay";
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};
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cpus {
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/*
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* Override the MPIDR value for simulator because MPIDR
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* value returned by the CPU on simulator is different
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* from the one in soc-base dtsi.
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*/
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cpu@0 {
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reg = <0x0 0x0>;
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};
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};
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gv11b {
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status = "okay";
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};
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mc {
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/delete-property/ ranges;
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/delete-node/ mssnvlink@1f20000;
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};
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};
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