forked from rrcarlosr/Jetpack
912 lines
26 KiB
Plaintext
912 lines
26 KiB
Plaintext
/*
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* Copyright (c) 2017 - 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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/ {
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pinmux@2430000 {
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pex_rst_c5_out_state: pex_rst_c5_out {
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pex_rst {
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nvidia,pins = "pex_l5_rst_n_pgg1";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,lpdr = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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};
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pex_rst_c5_in_state: pex_rst_c5_in {
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pex_rst {
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nvidia,pins = "pex_l5_rst_n_pgg1";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,lpdr = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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};
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clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
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clkreq {
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nvidia,pins = "pex_l5_clkreq_n_pgg0";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,lpdr = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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};
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};
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hsio_p2u {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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p2u_0: p2u@03e10000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e10000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 336 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <0>;
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#phy-cells = <0>;
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};
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p2u_1: p2u@03e20000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e20000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 337 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <1>;
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#phy-cells = <0>;
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};
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p2u_2: p2u@03e30000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e30000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 338 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <2>;
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#phy-cells = <0>;
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};
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p2u_3: p2u@03e40000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e40000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 339 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <3>;
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#phy-cells = <0>;
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};
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p2u_4: p2u@03e50000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e50000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 340 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <4>;
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#phy-cells = <0>;
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};
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p2u_5: p2u@03e60000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e60000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 341 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <5>;
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#phy-cells = <0>;
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};
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p2u_6: p2u@03e70000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e70000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 342 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <6>;
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#phy-cells = <0>;
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};
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p2u_7: p2u@03e80000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e80000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 343 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <7>;
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#phy-cells = <0>;
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};
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p2u_8: p2u@03e90000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03e90000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 344 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <8>;
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#phy-cells = <0>;
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};
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p2u_9: p2u@03ea0000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03ea0000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 345 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <9>;
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#phy-cells = <0>;
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};
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p2u_10: p2u@03f30000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03f30000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 221 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <10>;
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#phy-cells = <0>;
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};
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p2u_11: p2u@03f40000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03f40000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 222 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <11>;
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#phy-cells = <0>;
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};
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};
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nvhs_p2u {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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p2u_12: p2u@03eb0000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03eb0000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 346 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <12>;
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#phy-cells = <0>;
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};
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p2u_13: p2u@03ec0000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03ec0000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 347 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <13>;
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#phy-cells = <0>;
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};
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p2u_14: p2u@03ed0000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03ed0000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 348 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <14>;
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#phy-cells = <0>;
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};
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p2u_15: p2u@03ee0000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03ee0000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 349 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <15>;
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#phy-cells = <0>;
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};
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p2u_16: p2u@03ef0000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03ef0000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 350 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <16>;
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#phy-cells = <0>;
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};
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p2u_17: p2u@03f00000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03f00000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 351 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <17>;
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#phy-cells = <0>;
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};
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p2u_18: p2u@03f10000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03f10000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 203 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <18>;
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#phy-cells = <0>;
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};
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p2u_19: p2u@03f20000 {
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compatible = "nvidia,phy-p2u";
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reg = <0x0 0x03f20000 0x0 0x00010000>;
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reg-names = "base";
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interrupts = <0 220 0x04>;
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interrupt-names = "intr";
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nvidia,uphy-id = <19>;
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#phy-cells = <0>;
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};
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};
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pcie_ep@14180000 {
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compatible = "nvidia,tegra194-pcie-ep";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
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reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x38000000 0x0 0x02000000 /* window1 (32M) */
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0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
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0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
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0x18 0x00000000 0x4 0x00000000>; /* window2 (16G) */
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reg-names = "appl", "window1", "config", "atu_dma", "window2";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_0>;
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clock-names = "core_clk";
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resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_0_APB>,
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<&bpmp_resets TEGRA194_RESET_PEX0_CORE_0>;
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reset-names = "core_apb_rst", "core_rst";
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interrupts = <0 72 0x04>; /* controller interrupt */
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interrupt-names = "intr";
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nvidia,max-speed = <4>;
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nvidia,bar0-size = <0x100000>; /* 1 MB */
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nvidia,device-id = /bits/ 16 <0x1AD4>;
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nvidia,controller-id = <&bpmp 0x0>;
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num-lanes = <8>;
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nvidia,aux-clk-freq = <0x13>;
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nvidia,aspm-cmrt = <0x3C>;
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nvidia,aspm-pwr-on-t = <0x14>;
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nvidia,aspm-l0s-entrance-latency = <0x3>;
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nvidia,aspm-l1-entrance-latency = <0x5>;
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num-ib-windows = <2>;
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num-ob-windows = <8>;
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nvidia,margin-port-cap = <0x194>;
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nvidia,margin-lane-cntrl = <0x198>;
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nvidia,cfg-link-cap-l1sub = <0x1c4>;
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nvidia,event-cntr-ctrl = <0x1d8>;
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nvidia,event-cntr-data = <0x1dc>;
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nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000
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204000000 204000000 408000000 666000000
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204000000 408000000 666000000 1066000000
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408000000 666000000 1066000000 2133000000 >;
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iommus = <&smmu TEGRA_SID_PCIE0>;
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dma-coherent;
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#if LINUX_VERSION >= 414
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iommu-map = <0x0 &smmu TEGRA_SID_PCIE0 0x1000>;
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iommu-map-mask = <0x0>;
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#endif
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};
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pcie_ep@14160000 {
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compatible = "nvidia,tegra194-pcie-ep";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
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reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x36000000 0x0 0x02000000 /* window1 (32M) */
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0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
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0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
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0x14 0x00000000 0x4 0x00000000>; /* window2 (16G) */
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reg-names = "appl", "window1", "config", "atu_dma", "window2";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_4>;
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clock-names = "core_clk";
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resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_4_APB>,
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<&bpmp_resets TEGRA194_RESET_PEX0_CORE_4>;
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reset-names = "core_apb_rst", "core_rst";
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interrupts = <0 51 0x04>; /* controller interrupt */
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interrupt-names = "intr";
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nvidia,max-speed = <4>;
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nvidia,bar0-size = <0x100000>; /* 1 MB */
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nvidia,device-id = /bits/ 16 <0x1AD5>;
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nvidia,controller-id = <&bpmp 0x4>;
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num-lanes = <4>;
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nvidia,aux-clk-freq = <0x13>;
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nvidia,aspm-cmrt = <0x3C>;
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nvidia,aspm-pwr-on-t = <0x14>;
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nvidia,aspm-l0s-entrance-latency = <0x3>;
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nvidia,aspm-l1-entrance-latency = <0x5>;
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num-ib-windows = <2>;
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num-ob-windows = <8>;
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nvidia,margin-port-cap = <0x190>;
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nvidia,margin-lane-cntrl = <0x194>;
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nvidia,cfg-link-cap-l1sub = <0x1b0>;
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nvidia,event-cntr-ctrl = <0x1c4>;
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nvidia,event-cntr-data = <0x1c8>;
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nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000
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204000000 204000000 408000000 800000000
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204000000 408000000 800000000 1600000000
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0 0 0 0 >;
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iommus = <&smmu TEGRA_SID_PCIE4>;
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dma-coherent;
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#if LINUX_VERSION >= 414
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iommu-map = <0x0 &smmu TEGRA_SID_PCIE4 0x1000>;
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iommu-map-mask = <0x0>;
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#endif
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};
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pcie_ep@141a0000 {
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compatible = "nvidia,tegra194-pcie-ep";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
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reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x3a000000 0x0 0x02000000 /* window1 (32M) */
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0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
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0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
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0x1c 0x00000000 0x4 0x00000000>; /* window2 (16G) */
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reg-names = "appl", "window1", "config", "atu_dma", "window2";
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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clocks = <&bpmp_clks TEGRA194_CLK_PEX1_CORE_5>;
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clock-names = "core_clk";
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resets = <&bpmp_resets TEGRA194_RESET_PEX1_CORE_5_APB>,
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<&bpmp_resets TEGRA194_RESET_PEX1_CORE_5>;
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reset-names = "core_apb_rst", "core_rst";
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interrupts = <0 53 0x04>; /* controller interrupt */
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interrupt-names = "intr";
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pinctrl-names = "pex_rst", "clkreq";
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pinctrl-0 = <&pex_rst_c5_in_state>;
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pinctrl-1 = <&clkreq_c5_bi_dir_state>;
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nvidia,max-speed = <4>;
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nvidia,bar0-size = <0x100000>; /* 1 MB */
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nvidia,device-id = /bits/ 16 <0x1AD4>;
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nvidia,controller-id = <&bpmp 0x5>;
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num-lanes = <8>;
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nvidia,tsa-config = <0x0200b004>;
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nvidia,aux-clk-freq = <0x13>;
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nvidia,aspm-cmrt = <0x3C>;
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nvidia,aspm-pwr-on-t = <0x14>;
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nvidia,aspm-l0s-entrance-latency = <0x3>;
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nvidia,aspm-l1-entrance-latency = <0x5>;
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nvidia,host1x = <&host1x>;
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num-ib-windows = <2>;
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num-ob-windows = <8>;
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nvidia,margin-port-cap = <0x194>;
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nvidia,margin-lane-cntrl = <0x198>;
|
|
nvidia,cfg-link-cap-l1sub = <0x1c4>;
|
|
nvidia,event-cntr-ctrl = <0x1d8>;
|
|
nvidia,event-cntr-data = <0x1dc>;
|
|
|
|
nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000
|
|
204000000 204000000 408000000 666000000
|
|
204000000 408000000 666000000 1066000000
|
|
408000000 666000000 1066000000 2133000000 >;
|
|
|
|
iommus = <&smmu TEGRA_SID_PCIE5>;
|
|
dma-coherent;
|
|
#if LINUX_VERSION >= 414
|
|
iommu-map = <0x0 &smmu TEGRA_SID_PCIE5 0x1000>;
|
|
iommu-map-mask = <0x0>;
|
|
#endif
|
|
};
|
|
|
|
pcie@14180000 {
|
|
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
|
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
|
|
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
|
|
0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
|
|
reg-names = "appl", "config", "atu_dma";
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <8>;
|
|
linux,pci-domain = <0>;
|
|
|
|
clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_0>,
|
|
<&bpmp_clks TEGRA194_CLK_PEX0_CORE_0M>;
|
|
clock-names = "core_clk", "core_clk_m";
|
|
|
|
resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_0_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_0>;
|
|
reset-names = "core_apb_rst", "core_rst";
|
|
|
|
interrupts = <0 72 0x04>, /* controller interrupt */
|
|
<0 73 0x04>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
iommus = <&smmu TEGRA_SID_PCIE0>;
|
|
dma-coherent;
|
|
#if LINUX_VERSION >= 414
|
|
iommu-map = <0x0 &smmu TEGRA_SID_PCIE0 0x1000>;
|
|
iommu-map-mask = <0x0>;
|
|
#endif
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 0 72 0x04>;
|
|
|
|
nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000
|
|
204000000 204000000 408000000 666000000
|
|
204000000 408000000 666000000 1066000000
|
|
408000000 666000000 1066000000 2133000000 >;
|
|
nvidia,max-speed = <4>;
|
|
nvidia,disable-aspm-states = <0xf>;
|
|
nvidia,controller-id = <&bpmp 0x0>;
|
|
nvidia,disable-l1-cpm;
|
|
nvidia,aux-clk-freq = <0x13>;
|
|
nvidia,preset-init = <0x5>;
|
|
nvidia,aspm-cmrt = <0x3C>;
|
|
nvidia,aspm-pwr-on-t = <0x14>;
|
|
nvidia,aspm-l0s-entrance-latency = <0x3>;
|
|
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
|
0x82000000 0x0 0x40000000 0x1B 0x40000000 0x0 0xC0000000 /* non-prefetchable memory (3GB) */
|
|
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>; /* prefetchable memory (13GB) */
|
|
|
|
nvidia,cfg-link-cap-l1sub = <0x1c4>;
|
|
nvidia,cap-pl16g-status = <0x174>;
|
|
nvidia,cap-pl16g-cap-off = <0x188>;
|
|
nvidia,event-cntr-ctrl = <0x1d8>;
|
|
nvidia,event-cntr-data = <0x1dc>;
|
|
nvidia,margin-port-cap = <0x194>;
|
|
nvidia,margin-lane-cntrl = <0x198>;
|
|
nvidia,dl-feature-cap = <0x30c>;
|
|
};
|
|
|
|
pcie@14100000 {
|
|
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
|
reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
|
|
0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
|
|
0x00 0x30040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
|
|
reg-names = "appl", "config", "atu_dma";
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <1>;
|
|
linux,pci-domain = <1>;
|
|
|
|
clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_1>,
|
|
<&bpmp_clks TEGRA194_CLK_PEX0_CORE_1M>;
|
|
clock-names = "core_clk", "core_clk_m";
|
|
|
|
resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_1_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_1>;
|
|
reset-names = "core_apb_rst", "core_rst";
|
|
|
|
interrupts = <0 45 0x04>, /* controller interrupt */
|
|
<0 46 0x04>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
iommus = <&smmu TEGRA_SID_PCIE1>;
|
|
dma-coherent;
|
|
#if LINUX_VERSION >= 414
|
|
iommu-map = <0x0 &smmu TEGRA_SID_PCIE1 0x1000>;
|
|
iommu-map-mask = <0x0>;
|
|
#endif
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 0 45 0x04>;
|
|
|
|
nvidia,dvfs-tbl = < 204000000 408000000 800000000 1333000000
|
|
0 0 0 0
|
|
0 0 0 0
|
|
0 0 0 0 >;
|
|
|
|
nvidia,max-speed = <4>;
|
|
nvidia,disable-aspm-states = <0xf>;
|
|
nvidia,controller-id = <&bpmp 0x1>;
|
|
nvidia,host1x = <&host1x>;
|
|
nvidia,disable-l1-cpm;
|
|
nvidia,aux-clk-freq = <0x13>;
|
|
nvidia,preset-init = <0x5>;
|
|
nvidia,aspm-cmrt = <0x3C>;
|
|
nvidia,aspm-pwr-on-t = <0x14>;
|
|
nvidia,aspm-l0s-entrance-latency = <0x3>;
|
|
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
|
0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000 /* non-prefetchable memory (256MB) */
|
|
0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>; /* prefetchable memory (768MB) */
|
|
|
|
nvidia,cfg-link-cap-l1sub = <0x194>;
|
|
nvidia,cap-pl16g-status = <0x164>;
|
|
nvidia,cap-pl16g-cap-off = <0x178>;
|
|
nvidia,event-cntr-ctrl = <0x1a8>;
|
|
nvidia,event-cntr-data = <0x1ac>;
|
|
nvidia,margin-port-cap = <0x180>;
|
|
nvidia,margin-lane-cntrl = <0x184>;
|
|
nvidia,dl-feature-cap = <0x2dc>;
|
|
};
|
|
|
|
pcie@14120000 {
|
|
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
|
reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
|
|
0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
|
|
0x00 0x32040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
|
|
reg-names = "appl", "config", "atu_dma";
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <1>;
|
|
linux,pci-domain = <2>;
|
|
|
|
clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_2>,
|
|
<&bpmp_clks TEGRA194_CLK_PEX0_CORE_2M>;
|
|
clock-names = "core_clk", "core_clk_m";
|
|
|
|
resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_2_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_2>;
|
|
reset-names = "core_apb_rst", "core_rst";
|
|
|
|
interrupts = <0 47 0x04>, /* controller interrupt */
|
|
<0 48 0x04>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
iommus = <&smmu TEGRA_SID_PCIE2>;
|
|
dma-coherent;
|
|
#if LINUX_VERSION >= 414
|
|
iommu-map = <0x0 &smmu TEGRA_SID_PCIE2 0x1000>;
|
|
iommu-map-mask = <0x0>;
|
|
#endif
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 0 47 0x04>;
|
|
|
|
nvidia,dvfs-tbl = < 204000000 408000000 800000000 1333000000
|
|
0 0 0 0
|
|
0 0 0 0
|
|
0 0 0 0 >;
|
|
|
|
nvidia,max-speed = <4>;
|
|
nvidia,disable-aspm-states = <0xf>;
|
|
nvidia,controller-id = <&bpmp 0x2>;
|
|
nvidia,disable-l1-cpm;
|
|
nvidia,aux-clk-freq = <0x13>;
|
|
nvidia,preset-init = <0x5>;
|
|
nvidia,aspm-cmrt = <0x3C>;
|
|
nvidia,aspm-pwr-on-t = <0x14>;
|
|
nvidia,aspm-l0s-entrance-latency = <0x3>;
|
|
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
|
0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000 /* non-prefetchable memory (256MB) */
|
|
0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>; /* prefetchable memory (768MB) */
|
|
|
|
nvidia,cfg-link-cap-l1sub = <0x194>;
|
|
nvidia,cap-pl16g-status = <0x164>;
|
|
nvidia,cap-pl16g-cap-off = <0x178>;
|
|
nvidia,event-cntr-ctrl = <0x1a8>;
|
|
nvidia,event-cntr-data = <0x1ac>;
|
|
nvidia,margin-port-cap = <0x180>;
|
|
nvidia,margin-lane-cntrl = <0x184>;
|
|
nvidia,dl-feature-cap = <0x2dc>;
|
|
};
|
|
|
|
pcie@14140000 {
|
|
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
|
|
reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
|
|
0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
|
|
0x00 0x34040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
|
|
reg-names = "appl", "config", "atu_dma";
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <1>;
|
|
linux,pci-domain = <3>;
|
|
|
|
clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_3>,
|
|
<&bpmp_clks TEGRA194_CLK_PEX0_CORE_3M>;
|
|
clock-names = "core_clk", "core_clk_m";
|
|
|
|
resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_3_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_3>;
|
|
reset-names = "core_apb_rst", "core_rst";
|
|
|
|
interrupts = <0 49 0x04>, /* controller interrupt */
|
|
<0 50 0x04>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
iommus = <&smmu TEGRA_SID_PCIE3>;
|
|
dma-coherent;
|
|
#if LINUX_VERSION >= 414
|
|
iommu-map = <0x0 &smmu TEGRA_SID_PCIE3 0x1000>;
|
|
iommu-map-mask = <0x0>;
|
|
#endif
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 0 49 0x04>;
|
|
|
|
nvidia,dvfs-tbl = < 204000000 408000000 800000000 1333000000
|
|
0 0 0 0
|
|
0 0 0 0
|
|
0 0 0 0 >;
|
|
|
|
nvidia,max-speed = <4>;
|
|
nvidia,disable-aspm-states = <0xf>;
|
|
nvidia,controller-id = <&bpmp 0x3>;
|
|
nvidia,disable-l1-cpm;
|
|
nvidia,aux-clk-freq = <0x13>;
|
|
nvidia,preset-init = <0x5>;
|
|
nvidia,aspm-cmrt = <0x3C>;
|
|
nvidia,aspm-pwr-on-t = <0x14>;
|
|
nvidia,aspm-l0s-entrance-latency = <0x3>;
|
|
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
|
0x82000000 0x0 0x40000000 0x12 0xB0000000 0x0 0x10000000 /* non-prefetchable memory (256MB) */
|
|
0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>; /* prefetchable memory (768MB) */
|
|
|
|
nvidia,cfg-link-cap-l1sub = <0x194>;
|
|
nvidia,cap-pl16g-status = <0x164>;
|
|
nvidia,cap-pl16g-cap-off = <0x178>;
|
|
nvidia,event-cntr-ctrl = <0x1a8>;
|
|
nvidia,event-cntr-data = <0x1ac>;
|
|
nvidia,margin-port-cap = <0x180>;
|
|
nvidia,margin-lane-cntrl = <0x184>;
|
|
nvidia,dl-feature-cap = <0x2dc>;
|
|
};
|
|
|
|
pcie@14160000 {
|
|
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
|
|
reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
|
|
0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
|
|
0x00 0x36040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
|
|
reg-names = "appl", "config", "atu_dma";
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <4>;
|
|
linux,pci-domain = <4>;
|
|
|
|
clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_4>,
|
|
<&bpmp_clks TEGRA194_CLK_PEX0_CORE_4M>;
|
|
clock-names = "core_clk", "core_clk_m";
|
|
|
|
resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_4_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_4>;
|
|
reset-names = "core_apb_rst", "core_rst";
|
|
|
|
interrupts = <0 51 0x04>, /* controller interrupt */
|
|
<0 52 0x04>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
iommus = <&smmu TEGRA_SID_PCIE4>;
|
|
dma-coherent;
|
|
#if LINUX_VERSION >= 414
|
|
iommu-map = <0x0 &smmu TEGRA_SID_PCIE4 0x1000>;
|
|
iommu-map-mask = <0x0>;
|
|
#endif
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 0 51 0x04>;
|
|
|
|
nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000
|
|
204000000 204000000 408000000 800000000
|
|
204000000 408000000 800000000 1600000000
|
|
0 0 0 0 >;
|
|
|
|
nvidia,max-speed = <4>;
|
|
nvidia,disable-aspm-states = <0xf>;
|
|
nvidia,controller-id = <&bpmp 0x4>;
|
|
nvidia,disable-l1-cpm;
|
|
nvidia,aux-clk-freq = <0x13>;
|
|
nvidia,preset-init = <0x5>;
|
|
nvidia,aspm-cmrt = <0x3C>;
|
|
nvidia,aspm-pwr-on-t = <0x14>;
|
|
nvidia,aspm-l0s-entrance-latency = <0x3>;
|
|
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
|
0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xC0000000 /* non-prefetchable memory (3GB) */
|
|
0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>; /* prefetchable memory (13GB) */
|
|
|
|
nvidia,cfg-link-cap-l1sub = <0x1b0>;
|
|
nvidia,cap-pl16g-status = <0x174>;
|
|
nvidia,cap-pl16g-cap-off = <0x188>;
|
|
nvidia,event-cntr-ctrl = <0x1c4>;
|
|
nvidia,event-cntr-data = <0x1c8>;
|
|
nvidia,margin-port-cap = <0x190>;
|
|
nvidia,margin-lane-cntrl = <0x194>;
|
|
nvidia,dl-feature-cap = <0x2f8>;
|
|
};
|
|
|
|
pcie@141a0000 {
|
|
compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
|
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
|
|
0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
|
|
0x00 0x3a040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
|
|
reg-names = "appl", "config", "atu_dma";
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
num-lanes = <8>;
|
|
linux,pci-domain = <5>;
|
|
|
|
clocks = <&bpmp_clks TEGRA194_CLK_PEX1_CORE_5>,
|
|
<&bpmp_clks TEGRA194_CLK_PEX1_CORE_5M>;
|
|
clock-names = "core_clk", "core_clk_m";
|
|
|
|
resets = <&bpmp_resets TEGRA194_RESET_PEX1_CORE_5_APB>,
|
|
<&bpmp_resets TEGRA194_RESET_PEX1_CORE_5>;
|
|
reset-names = "core_apb_rst", "core_rst";
|
|
|
|
interrupts = <0 53 0x04>, /* controller interrupt */
|
|
<0 54 0x04>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
pinctrl-names = "pex_rst", "clkreq";
|
|
pinctrl-0 = <&pex_rst_c5_out_state>;
|
|
pinctrl-1 = <&clkreq_c5_bi_dir_state>;
|
|
|
|
iommus = <&smmu TEGRA_SID_PCIE5>;
|
|
dma-coherent;
|
|
#if LINUX_VERSION >= 414
|
|
iommu-map = <0x0 &smmu TEGRA_SID_PCIE5 0x1000>;
|
|
iommu-map-mask = <0x0>;
|
|
#endif
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &intc 0 53 0x04>;
|
|
|
|
nvidia,dvfs-tbl = < 204000000 204000000 204000000 408000000
|
|
204000000 204000000 408000000 666000000
|
|
204000000 408000000 666000000 1066000000
|
|
408000000 666000000 1066000000 2133000000 >;
|
|
|
|
nvidia,max-speed = <4>;
|
|
nvidia,disable-aspm-states = <0xf>;
|
|
nvidia,controller-id = <&bpmp 0x5>;
|
|
nvidia,tsa-config = <0x0200b004>;
|
|
nvidia,disable-l1-cpm;
|
|
nvidia,aux-clk-freq = <0x13>;
|
|
nvidia,preset-init = <0x5>;
|
|
nvidia,aspm-cmrt = <0x3C>;
|
|
nvidia,aspm-pwr-on-t = <0x14>;
|
|
nvidia,aspm-l0s-entrance-latency = <0x3>;
|
|
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
|
|
0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xC0000000 /* non-prefetchable memory (3GB) */
|
|
0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>; /* prefetchable memory (13GB) */
|
|
|
|
nvidia,cfg-link-cap-l1sub = <0x1c4>;
|
|
nvidia,cap-pl16g-status = <0x174>;
|
|
nvidia,cap-pl16g-cap-off = <0x188>;
|
|
nvidia,event-cntr-ctrl = <0x1d8>;
|
|
nvidia,event-cntr-data = <0x1dc>;
|
|
nvidia,margin-port-cap = <0x194>;
|
|
nvidia,margin-lane-cntrl = <0x198>;
|
|
nvidia,dl-feature-cap = <0x30c>;
|
|
};
|
|
};
|