forked from rrcarlosr/Jetpack
81 lines
2.6 KiB
Plaintext
81 lines
2.6 KiB
Plaintext
/*
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* tegra194-soc-eqos.dtsi: Ethernet QOS DTSI file.
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*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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#define MAKE_EQOS_TRIP(name, temp, hyst) \
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eqos_##name: eqos-##name@temp { \
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temperature = <(temp)>; \
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hysteresis = <hyst>; \
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type = "active"; \
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}
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#define MAP_EQOS(name, state) \
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map_eqos_##name { \
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trip = <&eqos_##name>; \
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cooling-device = <&eqos_cool_dev state state>; \
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cdev-type = "tegra-eqos"; \
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}
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/ {
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ether_qos@2490000 {
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compatible = "nvidia,eqos";
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reg = <0x0 0x02490000 0x0 0x10000>; /* EQOS Base Register */
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reg-names = "eqos_base";
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interrupts = <0 194 0x4>, /* common */
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<0 195 0x4>, /* power */
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<0 190 0x4>, /* rx0 */
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<0 186 0x4>, /* tx0 */
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<0 191 0x4>, /* rx1 */
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<0 187 0x4>, /* tx1 */
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<0 192 0x4>, /* rx2 */
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<0 188 0x4>, /* tx2 */
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<0 193 0x4>, /* rx3 */
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<0 189 0x4>; /* tx3 */
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clocks = <&bpmp_clks TEGRA194_CLK_PLLREFE_VCOOUT>,
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<&bpmp_clks TEGRA194_CLK_EQOS_AXI>,
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<&bpmp_clks TEGRA194_CLK_EQOS_RX>,
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<&bpmp_clks TEGRA194_CLK_EQOS_PTP_REF>,
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<&bpmp_clks TEGRA194_CLK_EQOS_TX>,
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<&bpmp_clks TEGRA194_CLK_AXI_CBB>;
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clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx", "eqos_ptp_ref", "eqos_tx", "axi_cbb";
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resets = <&bpmp_resets TEGRA194_RESET_EQOS>;
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reset-names = "eqos_rst";
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/* bootloader should update MAC address */
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nvidia,local-mac-address = <0x00 0x00 0x00 0x00 0x00 0x00>;
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iommus = <&smmu TEGRA_SID_EQOS>;
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iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
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dma-coherent;
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nvidia,csr_clock_speed = <0x19>; /* CSR clock speed 25MHz */
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nvidia,iso_bw = <81920>; /* sum of read and write bw, 80Mb/s */
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nvidia,rx_riwt = <124>; /* usec value for Rx watchdog interrupt */
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nvidia,slot_intvl_val = <0x07C>;
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status = "disabled";
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eqos_cool_dev: eqos-cool-dev {
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cooling-min-state = <0>;
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cooling-max-state = <5>;
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#cooling-cells = <2>;
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};
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};
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};
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