forked from rrcarlosr/Jetpack
270 lines
6.0 KiB
Plaintext
270 lines
6.0 KiB
Plaintext
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include "tegra194-cpuidle.dtsi"
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cl0_0>;
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};
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core1 {
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cpu = <&cl0_1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cl1_0>;
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};
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core1 {
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cpu = <&cl1_1>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cl2_0>;
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};
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core1 {
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cpu = <&cl2_1>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&cl3_0>;
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};
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core1 {
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cpu = <&cl3_1>;
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};
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};
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};
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cl0_0: cpu@0 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_0>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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};
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cl0_1: cpu@1 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x10001>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_0>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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status = "disabled";
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};
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cl1_0: cpu@2 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_1>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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status = "disabled";
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};
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cl1_1: cpu@3 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_1>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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status = "disabled";
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};
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cl2_0: cpu@4 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_2>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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status = "disabled";
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};
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cl2_1: cpu@5 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x201>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_2>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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status = "disabled";
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};
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cl3_0: cpu@6 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x10300>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_3>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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status = "disabled";
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};
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cl3_1: cpu@7 {
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device_type = "cpu";
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compatible = "nvidia,carmel", "arm,armv8";
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reg = <0x0 0x10301>;
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enable-method = "psci";
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cpu-idle-states = <&C6 &C7>;
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i-cache-size = <131072>;
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i-cache-line-size = <64>;
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i-cache-sets = <512>;
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d-cache-size = <65536>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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l2-cache = <&L2_3>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_CARMEL &CPU_COST_CARMEL>;
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status = "disabled";
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};
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};
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L2_0: l2-cache0 {
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cache-size = <2097152>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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next-level-cache = <&L3>;
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};
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L2_1: l2-cache1 {
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cache-size = <2097152>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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next-level-cache = <&L3>;
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status = "disabled";
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};
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L2_2: l2-cache2 {
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cache-size = <2097152>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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next-level-cache = <&L3>;
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status = "disabled";
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};
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L2_3: l2-cache3 {
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cache-size = <2097152>;
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cache-line-size = <64>;
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cache-sets = <2048>;
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next-level-cache = <&L3>;
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status = "disabled";
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};
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L3: l3-cache {
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cache-size = <4194304>;
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cache-line-size = <64>;
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cache-sets = <4096>;
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};
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CPU_COST_CARMEL: core-cost1 {
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busy-cost-data = <1024 1024>;
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idle-cost-data = <128>;
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};
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arm-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 384 0x4>,
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<0 385 0x4>,
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<0 386 0x4>,
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<0 387 0x4>,
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<0 388 0x4>,
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<0 389 0x4>,
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<0 390 0x4>,
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<0 391 0x4>;
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interrupt-affinity = <&cl0_0>,
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<&cl0_1>,
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<&cl1_0>,
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<&cl1_1>,
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<&cl2_0>,
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<&cl2_1>,
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<&cl3_0>,
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<&cl3_1>;
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status = "disabled";
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};
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carmel-pmu {
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compatible = "nvidia,carmel-pmu";
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interrupts = <0 365 0x4>;
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interrupt-affinity = <&{/cpus/cpu@0}>;
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status = "okay";
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};
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};
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