forked from rrcarlosr/Jetpack
136 lines
3.8 KiB
Plaintext
136 lines
3.8 KiB
Plaintext
/*
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* tegra194-camera.dtsi: Camera RTCPU DTSI file.
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*
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* Copyright (c) 2016-2018, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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/ {
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aliases { /* RCE is the Camera RTCPU */
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tegra-camera-rtcpu = &tegra_rce;
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};
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tegra_rce: rtcpu@bc00000 {
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compatible = "nvidia,tegra194-rce";
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nvidia,cpu-name = "rce";
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reg = <0 0xbc00000 0 0x1000>, /* RCE EVP (RCE_ATCM_EVP) */
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<0 0xb9f0000 0 0x40000>, /* RCE PM */
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<0 0xb840000 0 0x10000>,
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<0 0xb850000 0 0x10000>;
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reg-names = "rce-evp", "rce-pm",
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"ast-cpu", "ast-dma";
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clocks =
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<&bpmp_clks TEGRA194_CLK_RCE_CPU_NIC>,
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<&bpmp_clks TEGRA194_CLK_RCE_NIC>;
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clock-names = "rce-cpu-nic", "rce-nic";
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nvidia,clock-rates =
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<19200000 370000000>,
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<19200000 370000000>;
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nvidia,clock-parents =
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<&bpmp_clks TEGRA194_CLK_CLK_M>,
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<&bpmp_clks TEGRA194_CLK_NAFLL_RCE>;
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nvidia,clock-parent-names = "clk-m", "nafll-rce";
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resets = <&bpmp_resets TEGRA194_RESET_RCE_ALL>;
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reset-names = "rce-all";
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interrupts = <0 TEGRA194_IRQ_RCE_WDT_REMOTE 0x4>;
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interrupt-names = "wdt-remote";
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nvidia,camera-devices = <&isp &vi &nvcsi>;
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nvidia,camera-device-names = "isp", "vi", "nvcsi";
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/* Max EMC bandwidth, used during initializing RCE */
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nvidia,memory-bw = <0xffffffff>;
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iommus = <&smmu TEGRA_SID_RCE>;
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iommu-resv-regions = <0x0 0x0 0x0 0xA0000000 0x0 0xc0000000 0xffffffff 0xffffffff>;
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dma-coherent;
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nvidia,trace = <&{/tegra-rtcpu-trace} 4 0x70100000 0x100000>;
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nvidia,ivc-channels = <&{/camera-ivc-channels} 2 0x90000000 0x10000>;
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nvidia,autosuspend-delay-ms = <5000>;
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hsp {
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compatible = "nvidia,tegra186-hsp-mailbox";
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nvidia,hsp-shared-mailbox = <&hsp_rce 1 &hsp_rce 6>;
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nvidia,hsp-shared-mailbox-names = "ivc-pair", "cmd-pair";
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};
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};
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camera-ivc-channels {
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echo@0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-echo";
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nvidia,service = "echo";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <64>;
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};
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dbg@1 {
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/* This is raw channel exposed as device */
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compatible = "nvidia,tegra186-camera-ivc-protocol-dbg";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <384>;
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};
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dbg@2 {
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/* This is exposed in debugfs */
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compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <8192>;
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nvidia,ivc-timeout = <50>;
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nvidia,test-timeout = <5000>;
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nvidia,mem-map = <&tegra_rce &vi &isp>;
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/* Max EMC bandwidth during tests */
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nvidia,test-bw = <0xffFFffFF>;
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};
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ivccontrol@3 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
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nvidia,service = "capture-control";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <64>;
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nvidia,frame-size = <320>;
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};
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ivccapture@4 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
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nvidia,service = "capture";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <512>;
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nvidia,frame-size = <64>;
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};
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};
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tegra-rtcpu-trace {
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nvidia,enable-printk;
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nvidia,interval-ms = <50>;
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nvidia,log-prefix = "[RCE]";
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};
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};
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