forked from rrcarlosr/Jetpack
373 lines
8.9 KiB
Plaintext
373 lines
8.9 KiB
Plaintext
/*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "dt-bindings/clock/tegra194-clock.h"
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#define CAM0_RST_L TEGRA194_MAIN_GPIO(H, 3)
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#define CAM0_PWDN TEGRA194_MAIN_GPIO(H, 6)
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#define CAM1_RST_L TEGRA194_MAIN_GPIO(T, 6)
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#define CAM1_PWDN TEGRA194_MAIN_GPIO(T, 5)
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#define CAMERA_I2C_MUX_BUS(x) (0x1E + x)
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/ {
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nvidia,dtsfilename = __FILE__;
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nvidia,dtbbuildtime = __DATE__, __TIME__;
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gpio@2200000 {
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camera-control-output-low {
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gpio-hog;
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output-low;
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gpios = <CAM0_RST_L 0 CAM0_PWDN 0
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CAM1_RST_L 0 CAM1_PWDN 0>;
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label = "cam0-rst", "cam0-pwdn",
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"cam1-rst", "cam1-pwdn";
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};
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};
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host1x {
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vi@15c10000 {
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status = "okay";
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num-channels = <2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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status ="okay";
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reg = <0>;
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avt_csi2_vi_in0: endpoint {
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status = "okay";
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port-index = <0>;
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bus-width = <4>;
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remote-endpoint = <&avt_csi2_csi_out0>;
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};
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};
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port@1 {
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status ="okay";
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reg = <1>;
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avt_csi2_vi_in1: endpoint {
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status = "okay";
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port-index = <2>;
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bus-width = <4>;
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remote-endpoint = <&avt_csi2_csi_out1>;
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};
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};
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};
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};
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nvcsi@15a00000 {
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status = "okay";
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num-channels = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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status = "okay";
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reg = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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status = "okay";
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reg = <0>;
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avt_csi2_csi_in0: endpoint@0 {
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status = "okay";
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port-index = <0>;
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bus-width = <4>;
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remote-endpoint = <&avt_csi2_out0>;
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};
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};
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port@1 {
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status = "okay";
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reg = <1>;
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avt_csi2_csi_out0: endpoint@1 {
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status = "okay";
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remote-endpoint = <&avt_csi2_vi_in0>;
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};
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};
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};
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};
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channel@1 {
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status = "okay";
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reg = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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status = "okay";
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reg = <0>;
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avt_csi2_csi_in1: endpoint@0 {
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status = "okay";
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port-index = <2>;
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bus-width = <4>;
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remote-endpoint = <&avt_csi2_out1>;
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};
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};
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port@1 {
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status = "okay";
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reg = <1>;
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avt_csi2_csi_out1: endpoint@1 {
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status = "okay";
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remote-endpoint = <&avt_csi2_vi_in1>;
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};
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};
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};
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};
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};
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};
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tegra-camera-platform {
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compatible = "nvidia, tegra-camera-platform";
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status = "okay";
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/**
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* Physical settings to calculate max ISO BW
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*
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* num_csi_lanes = <>;
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* Total number of CSI lanes when all cameras are active
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*
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* max_lane_speed = <>;
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* Max lane speed in Kbit/s
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*
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* min_bits_per_pixel = <>;
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* Min bits per pixel
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*
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* vi_peak_byte_per_pixel = <>;
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* Max byte per pixel for the VI ISO case
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*
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* vi_bw_margin_pct = <>;
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* Vi bandwidth margin in percentage
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*
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* max_pixel_rate = <>;
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* Max pixel rate in Kpixel/s for the ISP ISO case
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*
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* isp_peak_byte_per_pixel = <>;
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* Max byte per pixel for the ISP ISO case
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*
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* isp_bw_margin_pct = <>;
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* Isp bandwidth margin in percentage
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*/
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num_csi_lanes = <8>;
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max_lane_speed = <1500000>;
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min_bits_per_pixel = <8>;
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vi_peak_byte_per_pixel = <2>;
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vi_bw_margin_pct = <25>;
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max_pixel_rate = <160000>;
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isp_peak_byte_per_pixel = <5>;
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isp_bw_margin_pct = <25>;
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/**
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* The general guideline for naming badge_info contains 3 parts, and is as follows,
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* The first part is the camera_board_id for the module; if the module is in a FFD
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* platform, then use the platform name for this part.
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* The second part contains the position of the module, ex. “rear” or “front”.
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* The third part contains the last 6 characters of a part number which is found
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* in the module's specsheet from the vender.
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*/
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modules {
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status = "okay";
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module0 {
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status = "okay";
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badge = "avt_csi2";
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position = "front";
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orientation = "1";
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drivernode0 {
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status = "okay";
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/* Declare PCL support driver (classically known as guid) */
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pcl_id = "v4l2_sensor";
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/* Driver v4l2 device name */
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devname = "avt_csi2 2-003c";
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/* Declare the device-tree hierarchy to driver instance */
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proc-device-tree = "/proc/device-tree/i2c@3180000/avt_csi2@3c";
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};
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};
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module1 {
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status = "okay";
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badge = "avt_csi2";
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position = "back";
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orientation = "1";
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drivernode0 {
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status = "okay";
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/* Declare PCL support driver (classically known as guid) */
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pcl_id = "v4l2_sensor";
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/* Driver v4l2 device name */
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devname = "avt_csi2 7-003c";
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/* Declare the device-tree hierarchy to driver instance */
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proc-device-tree = "/proc/device-tree/i2c@c250000/avt_csi2@3c";
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};
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};
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};
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};
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i2c@3180000 {
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avt_csi2@3c {
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status = "okay";
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clocks = <&bpmp_clks TEGRA194_CLK_EXTPERIPH1>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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devnode = "video0";
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compatible = "alliedvision,avt_csi2";
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reg = <0x3c>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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avt_csi2_out0: endpoint {
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port-index = <0>;
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bus-width = <4>;
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remote-endpoint = <&avt_csi2_csi_in0>;
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};
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};
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};
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mode0 {
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num_lanes = "4";
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tegra_sinterface = "serial_a";
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discontinuous_clk = "no";
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cil_settletime = "0";
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embedded_metadata_height = "0";
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/* not verified: */
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mclk_khz = "24000";
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phy_mode = "DPHY";
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dpcm_enable = "false";
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active_w = "5488";
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active_h = "4112";
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pixel_t = "bayer_bggr";
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readout_orientation = "0";
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line_length = "5488";
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inherent_gain = "1";
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mclk_multiplier = "31.25";
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pix_clk_hz = "750000000";
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gain_factor = "16";
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framerate_factor = "1000000";
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exposure_factor = "1000000";
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min_gain_val = "16"; /* 1.0 */
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max_gain_val = "256"; /* 16.0 */
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step_gain_val = "1"; /* 0.125 */
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min_hdr_ratio = "1";
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max_hdr_ratio = "64";
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min_framerate = "1500000"; /* 1.5 */
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max_framerate = "30000000"; /* 30 */
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step_framerate = "1";
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min_exp_time = "34"; /* us */
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max_exp_time = "550385"; /* us */
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step_exp_time = "1";
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};
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};
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};
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i2c@c250000 {
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pinctrl-names = "default";
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pinctrl-0 = <&gen8_i2c_pinctrl>;
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avt_csi2@3c {
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status = "okay";
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clocks = <&bpmp_clks TEGRA194_CLK_EXTPERIPH1>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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devnode = "video1";
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compatible = "alliedvision,avt_csi2";
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reg = <0x3c>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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avt_csi2_out1: endpoint {
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port-index = <0>;
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bus-width = <4>;
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remote-endpoint = <&avt_csi2_csi_in1>;
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};
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};
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};
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mode0 {
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num_lanes = "4";
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tegra_sinterface = "serial_c";
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discontinuous_clk = "no";
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cil_settletime = "0";
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embedded_metadata_height = "0";
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/* not verified: */
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mclk_khz = "24000";
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phy_mode = "DPHY";
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dpcm_enable = "false";
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active_w = "5488";
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active_h = "4112";
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pixel_t = "bayer_bggr";
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readout_orientation = "0";
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line_length = "5488";
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inherent_gain = "1";
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mclk_multiplier = "31.25";
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pix_clk_hz = "750000000";
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gain_factor = "16";
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framerate_factor = "1000000";
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exposure_factor = "1000000";
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min_gain_val = "16"; /* 1.0 */
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max_gain_val = "256"; /* 16.0 */
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step_gain_val = "1"; /* 0.125 */
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min_hdr_ratio = "1";
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max_hdr_ratio = "64";
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min_framerate = "1500000"; /* 1.5 */
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max_framerate = "30000000"; /* 30 */
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step_framerate = "1";
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min_exp_time = "34"; /* us */
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max_exp_time = "550385"; /* us */
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step_exp_time = "1";
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};
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};
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};
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pinmux@2430000 {
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gen8_i2c_pinctrl: gen8_i2c_pinctrl {
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gen8_i2c_scl {
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nvidia,pins = "gen8_i2c_scl_pdd1";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,lpdr = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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gen8_i2c_sda {
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nvidia,pins = "gen8_i2c_sda_pdd2";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,lpdr = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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};
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};
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};
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