forked from rrcarlosr/Jetpack
30 lines
519 B
C
30 lines
519 B
C
/*
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* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __CLK_MICROCHIP_PIC32
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#define __CLK_MICROCHIP_PIC32
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/* clock output indices */
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#define BASECLK 0
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#define PLLCLK 1
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#define MPLL 2
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#define SYSCLK 3
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#define PB1CLK 4
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#define PB2CLK 5
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#define PB3CLK 6
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#define PB4CLK 7
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#define PB5CLK 8
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#define PB6CLK 9
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#define PB7CLK 10
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#define REF1CLK 11
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#define REF2CLK 12
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#define REF3CLK 13
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#define REF4CLK 14
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#define REF5CLK 15
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#endif /* __CLK_MICROCHIP_PIC32 */
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