forked from rrcarlosr/Jetpack
113 lines
3.6 KiB
C
113 lines
3.6 KiB
C
/*
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* include/asm-ppc/cache.h
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*/
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#ifndef __ARCH_PPC_CACHE_H
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#define __ARCH_PPC_CACHE_H
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#include <asm/processor.h>
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/* bytes per L1 cache line */
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#if defined(CONFIG_8xx)
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#define L1_CACHE_SHIFT 4
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#elif defined(CONFIG_PPC64BRIDGE)
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#define L1_CACHE_SHIFT 7
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#elif defined(CONFIG_E500MC)
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#define L1_CACHE_SHIFT 6
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#else
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#define L1_CACHE_SHIFT 5
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/*
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* Use the L1 data cache line size value for the minimum DMA buffer alignment
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* on PowerPC.
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*/
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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/*
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* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
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*/
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#ifndef CONFIG_SYS_CACHELINE_SIZE
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#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
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#endif
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#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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#define L1_CACHE_PAGES 8
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#ifdef MODULE
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#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
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#else
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#define __cacheline_aligned \
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__attribute__((__aligned__(L1_CACHE_BYTES), \
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__section__(".data.cacheline_aligned")))
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#endif
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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extern void flush_dcache_range(unsigned long start, unsigned long stop);
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extern void clean_dcache_range(unsigned long start, unsigned long stop);
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extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
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extern void flush_dcache(void);
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extern void invalidate_dcache(void);
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extern void invalidate_icache(void);
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#ifdef CONFIG_SYS_INIT_RAM_LOCK
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extern void unlock_ram_in_cache(void);
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#endif /* CONFIG_SYS_INIT_RAM_LOCK */
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#endif /* __ASSEMBLY__ */
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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int l2cache_init(void);
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void enable_cpc(void);
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void disable_cpc_sram(void);
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#endif
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/* prep registers for L2 */
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#define CACHECRBA 0x80000823 /* Cache configuration register address */
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#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
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#define L2CACHE_512KB 0x00 /* 512KB */
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#define L2CACHE_256KB 0x01 /* 256KB */
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#define L2CACHE_1MB 0x02 /* 1MB */
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#define L2CACHE_NONE 0x03 /* NONE */
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#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
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#ifdef CONFIG_8xx
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/* Cache control on the MPC8xx is provided through some additional
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* special purpose registers.
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*/
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#define IC_CST 560 /* Instruction cache control/status */
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#define IC_ADR 561 /* Address needed for some commands */
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#define IC_DAT 562 /* Read-only data register */
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#define DC_CST 568 /* Data cache control/status */
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#define DC_ADR 569 /* Address needed for some commands */
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#define DC_DAT 570 /* Read-only data register */
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/* Commands. Only the first few are available to the instruction cache.
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*/
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#define IDC_ENABLE 0x02000000 /* Cache enable */
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#define IDC_DISABLE 0x04000000 /* Cache disable */
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#define IDC_LDLCK 0x06000000 /* Load and lock */
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#define IDC_UNLINE 0x08000000 /* Unlock line */
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#define IDC_UNALL 0x0a000000 /* Unlock all */
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#define IDC_INVALL 0x0c000000 /* Invalidate all */
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#define DC_FLINE 0x0e000000 /* Flush data cache line */
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#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
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#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
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#define DC_SLES 0x05000000 /* Set little endian swap mode */
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#define DC_CLES 0x07000000 /* Clear little endian swap mode */
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/* Status.
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*/
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#define IDC_ENABLED 0x80000000 /* Cache is enabled */
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#define IDC_CERR1 0x00200000 /* Cache error 1 */
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#define IDC_CERR2 0x00100000 /* Cache error 2 */
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#define IDC_CERR3 0x00080000 /* Cache error 3 */
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#define DC_DFWT 0x40000000 /* Data cache is forced write through */
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#define DC_LES 0x20000000 /* Caches are little endian mode */
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#endif /* CONFIG_8xx */
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#endif
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