forked from rrcarlosr/Jetpack
263 lines
6.2 KiB
C
263 lines
6.2 KiB
C
/*
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* Clock drivers for Qualcomm APQ8016
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* Based on Little Kernel driver, simplified
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS 0x2101C
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#define GPLL0_STATUS_ACTIVE BIT(17)
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#define APCS_GPLL_ENA_VOTE 0x45000
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#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
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/* vote reg for blsp1 clock */
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#define APCS_CLOCK_BRANCH_ENA_VOTE 0x45004
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#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
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/* SDC(n) clock control registers; n=1,2 */
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/* block control register */
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#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
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/* cmd */
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#define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)
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/* cfg */
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#define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008)
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/* m */
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#define SDCC_M(n) ((n * 0x1000) + 0x4100C)
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/* n */
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#define SDCC_N(n) ((n * 0x1000) + 0x41010)
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/* d */
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#define SDCC_D(n) ((n * 0x1000) + 0x41014)
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/* branch control */
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#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
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#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
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/* BLSP1 AHB clock (root clock for BLSP) */
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#define BLSP1_AHB_CBCR 0x1008
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/* Uart clock control registers */
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#define BLSP1_UART2_BCR 0x3028
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#define BLSP1_UART2_APPS_CBCR 0x302C
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#define BLSP1_UART2_APPS_CMD_RCGR 0x3034
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#define BLSP1_UART2_APPS_CFG_RCGR 0x3038
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#define BLSP1_UART2_APPS_M 0x303C
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#define BLSP1_UART2_APPS_N 0x3040
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#define BLSP1_UART2_APPS_D 0x3044
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/* CBCR register fields */
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#define CBCR_BRANCH_ENABLE_BIT BIT(0)
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#define CBCR_BRANCH_OFF_BIT BIT(31)
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struct msm_clk_priv {
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phys_addr_t base;
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};
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/* Enable clock controlled by CBC soft macro */
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static void clk_enable_cbc(phys_addr_t cbcr)
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{
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setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
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while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
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;
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}
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/* clock has 800MHz */
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static void clk_enable_gpll0(phys_addr_t base)
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{
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if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE)
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return; /* clock already enabled */
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setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0);
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while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0)
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;
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}
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#define APPS_CMD_RGCR_UPDATE BIT(0)
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/* Update clock command via CMD_RGCR */
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static void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
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{
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setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
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/* Wait for frequency to be updated. */
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while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
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;
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}
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struct bcr_regs {
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uintptr_t cfg_rcgr;
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uintptr_t cmd_rcgr;
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uintptr_t M;
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uintptr_t N;
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uintptr_t D;
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};
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/* RCGR_CFG register fields */
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#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
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/* sources */
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#define CFG_CLK_SRC_CXO (0 << 8)
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#define CFG_CLK_SRC_GPLL0 (1 << 8)
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#define CFG_CLK_SRC_MASK (7 << 8)
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/* Mask for supported fields */
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#define CFG_MASK 0x3FFF
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#define CFG_DIVIDER_MASK 0x1F
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/* root set rate for clocks with half integer and MND divider */
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static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
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int div, int m, int n, int source)
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{
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uint32_t cfg;
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/* M value for MND divider. */
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uint32_t m_val = m;
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/* NOT(N-M) value for MND divider. */
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uint32_t n_val = ~((n)-(m)) * !!(n);
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/* NOT 2D value for MND divider. */
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uint32_t d_val = ~(n);
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/* Program MND values */
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writel(m_val, base + regs->M);
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writel(n_val, base + regs->N);
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writel(d_val, base + regs->D);
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/* setup src select and divider */
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cfg = readl(base + regs->cfg_rcgr);
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cfg &= ~CFG_MASK;
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cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
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/* Set the divider; HW permits fraction dividers (+0.5), but
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for simplicity, we will support integers only */
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if (div)
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cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
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if (n_val)
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cfg |= CFG_MODE_DUAL_EDGE;
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writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
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/* Inform h/w to start using the new config. */
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clk_bcr_update(base + regs->cmd_rcgr);
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}
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static const struct bcr_regs sdc_regs[] = {
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{
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.cfg_rcgr = SDCC_CFG_RCGR(1),
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.cmd_rcgr = SDCC_CMD_RCGR(1),
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.M = SDCC_M(1),
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.N = SDCC_N(1),
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.D = SDCC_D(1),
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},
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{
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.cfg_rcgr = SDCC_CFG_RCGR(2),
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.cmd_rcgr = SDCC_CMD_RCGR(2),
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.M = SDCC_M(2),
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.N = SDCC_N(2),
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.D = SDCC_D(2),
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}
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};
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/* Init clock for SDHCI controller */
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static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
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{
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int div = 8; /* 100MHz default */
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if (rate == 200000000)
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div = 4;
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clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
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/* 800Mhz/div, gpll0 */
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clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
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CFG_CLK_SRC_GPLL0);
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clk_enable_gpll0(priv->base);
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clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
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return rate;
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}
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static const struct bcr_regs uart2_regs = {
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.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
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.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
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.M = BLSP1_UART2_APPS_M,
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.N = BLSP1_UART2_APPS_N,
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.D = BLSP1_UART2_APPS_D,
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};
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/* Init UART clock, 115200 */
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static int clk_init_uart(struct msm_clk_priv *priv)
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{
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/* Enable iface clk */
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clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
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/* 7372800 uart block clock @ GPLL0 */
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clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
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CFG_CLK_SRC_GPLL0);
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clk_enable_gpll0(priv->base);
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/* Enable core clk */
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clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
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return 0;
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}
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ulong msm_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0: /* SDC1 */
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return clk_init_sdc(priv, 0, rate);
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break;
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case 1: /* SDC2 */
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return clk_init_sdc(priv, 1, rate);
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break;
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case 4: /* UART2 */
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return clk_init_uart(priv);
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break;
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default:
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return 0;
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}
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}
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static int msm_clk_probe(struct udevice *dev)
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{
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struct msm_clk_priv *priv = dev_get_priv(dev);
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priv->base = dev_get_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static struct clk_ops msm_clk_ops = {
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.set_rate = msm_set_rate,
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};
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static const struct udevice_id msm_clk_ids[] = {
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{ .compatible = "qcom,gcc-msm8916" },
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{ .compatible = "qcom,gcc-apq8016" },
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{ }
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};
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U_BOOT_DRIVER(clk_msm) = {
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.name = "clk_msm",
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.id = UCLASS_CLK,
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.of_match = msm_clk_ids,
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.ops = &msm_clk_ops,
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.priv_auto_alloc_size = sizeof(struct msm_clk_priv),
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.probe = msm_clk_probe,
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};
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