forked from rrcarlosr/Jetpack
879 lines
24 KiB
C
879 lines
24 KiB
C
/*
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* tegra210_adx_alt.c - Tegra210 ADX driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <soc/tegra/chip-id.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/of_device.h>
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#include "tegra210_xbar_alt.h"
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#include "tegra210_adx_alt.h"
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#define DRV_NAME "tegra210-adx"
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static const struct reg_default tegra210_adx_reg_defaults[] = {
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{ TEGRA210_ADX_AXBAR_RX_INT_MASK, 0x00000001},
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{ TEGRA210_ADX_AXBAR_RX_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_AXBAR_TX_INT_MASK, 0x0000000f },
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{ TEGRA210_ADX_AXBAR_TX1_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_AXBAR_TX2_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_AXBAR_TX3_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_AXBAR_TX4_CIF_CTRL, 0x00007000},
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{ TEGRA210_ADX_CG, 0x1},
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{ TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, 0x00004000},
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};
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/**
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* tegra210_adx_enable_outstream - enable output stream
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* @adx: struct of tegra210_adx
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* @stream_id: adx output stream id for enabling
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*/
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static void tegra210_adx_enable_outstream(struct tegra210_adx *adx,
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unsigned int stream_id)
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{
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int reg;
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reg = TEGRA210_ADX_CTRL;
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regmap_update_bits(adx->regmap, reg,
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TEGRA210_ADX_TX_ENABLE << stream_id,
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TEGRA210_ADX_TX_ENABLE << stream_id);
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}
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/**
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* tegra210_adx_disable_outstream - disable output stream
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* @adx: struct of tegra210_adx
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* @stream_id: adx output stream id for disabling
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*/
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static void tegra210_adx_disable_outstream(struct tegra210_adx *adx,
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unsigned int stream_id)
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{
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int reg;
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reg = TEGRA210_ADX_CTRL;
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regmap_update_bits(adx->regmap, reg,
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TEGRA210_ADX_TX_ENABLE << stream_id,
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TEGRA210_ADX_TX_DISABLE);
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}
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/**
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* tegra210_adx_set_in_byte_mask - set byte mask for input frame
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* @adx: struct of tegra210_adx
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* @mask1: enable for bytes 31 ~ 0 of input frame
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* @mask2: enable for bytes 63 ~ 32 of input frame
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*/
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static void tegra210_adx_set_in_byte_mask(struct tegra210_adx *adx)
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{
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regmap_write(adx->regmap,
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TEGRA210_ADX_IN_BYTE_EN0, adx->byte_mask[0]);
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regmap_write(adx->regmap,
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TEGRA210_ADX_IN_BYTE_EN1, adx->byte_mask[1]);
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}
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/**
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* tegra210_adx_set_map_table - set map table not RAM
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* @adx: struct of tegra210_adx
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* @out_byte_addr: byte address in one frame
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* @stream_id: input stream id
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* @nth_word: n-th word in the input stream
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* @nth_byte: n-th byte in the word
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*/
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static void tegra210_adx_set_map_table(struct tegra210_adx *adx,
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unsigned int out_byte_addr,
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unsigned int stream_id,
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unsigned int nth_word,
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unsigned int nth_byte)
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{
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unsigned char *bytes_map = (unsigned char *)&adx->map;
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bytes_map[out_byte_addr] =
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(stream_id << TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT) |
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(nth_word << TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT) |
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(nth_byte << TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT);
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}
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/**
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* tegra210_adx_write_map_ram - write map information in RAM
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* @adx: struct of tegra210_adx
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* @addr: n-th word of input stream
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* @val : bytes mapping information of the word
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*/
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static void tegra210_adx_write_map_ram(struct tegra210_adx *adx,
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unsigned int addr,
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unsigned int val)
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{
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unsigned int reg;
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regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL,
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(addr << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT));
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regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_DATA, val);
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regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, ®);
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reg |= TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN;
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regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, reg);
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regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, ®);
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reg |= TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_WRITE;
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regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, reg);
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}
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static void tegra210_adx_update_map_ram(struct tegra210_adx *adx)
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{
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int i;
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for (i = 0; i < TEGRA210_ADX_RAM_DEPTH; i++)
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tegra210_adx_write_map_ram(adx, i, adx->map[i]);
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}
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static int tegra210_adx_sw_reset(struct tegra210_adx *adx,
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int timeout)
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{
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unsigned int val;
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int wait = timeout;
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regmap_update_bits(adx->regmap, TEGRA210_ADX_SOFT_RESET,
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TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK,
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TEGRA210_ADX_SOFT_RESET_SOFT_EN);
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do {
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regmap_read(adx->regmap, TEGRA210_ADX_SOFT_RESET, &val);
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wait--;
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if (!wait)
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return -EINVAL;
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} while (val & 0x00000001);
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regmap_update_bits(adx->regmap, TEGRA210_ADX_SOFT_RESET,
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TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK,
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TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT);
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return 0;
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}
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static int tegra210_adx_get_status(struct tegra210_adx *adx)
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{
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unsigned int val;
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regmap_read(adx->regmap, TEGRA210_ADX_STATUS, &val);
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val = (val & 0x00000001);
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return val;
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}
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static int tegra210_adx_stop(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
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struct device *dev = codec->dev;
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struct tegra210_adx *adx = dev_get_drvdata(dev);
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int dcnt = 10, ret = 0;
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/* wait until ADX status is disabled */
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while (tegra210_adx_get_status(adx) && dcnt--)
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udelay(100);
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/* HW needs sw reset to make sure previous transaction be clean */
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ret = tegra210_adx_sw_reset(adx, 0xffff);
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if (ret) {
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dev_err(dev, "Failed at ADX%d sw reset\n", dev->id);
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return ret;
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}
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return (dcnt < 0) ? -ETIMEDOUT : 0;
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}
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static unsigned int __maybe_unused tegra210_adx_read_map_ram(
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struct tegra210_adx *adx,
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unsigned int addr)
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{
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unsigned int val, wait;
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wait = 0xffff;
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regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL,
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(addr << TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RAM_ADDR_SHIFT));
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regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, &val);
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val |= TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_ADDR_INIT_EN;
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regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, val);
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regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, &val);
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val &= ~(TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL_RW_WRITE);
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regmap_write(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, val);
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do {
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regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL, &val);
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wait--;
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if (!wait)
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return -EINVAL;
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} while (val & 0x80000000);
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regmap_read(adx->regmap, TEGRA210_ADX_AHUBRAMCTL_ADX_DATA, &val);
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return val;
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}
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static int tegra210_adx_runtime_suspend(struct device *dev)
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{
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struct tegra210_adx *adx = dev_get_drvdata(dev);
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regcache_cache_only(adx->regmap, true);
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regcache_mark_dirty(adx->regmap);
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return 0;
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}
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static int tegra210_adx_runtime_resume(struct device *dev)
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{
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struct tegra210_adx *adx = dev_get_drvdata(dev);
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regcache_cache_only(adx->regmap, false);
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regcache_sync(adx->regmap);
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/* update the map ram */
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tegra210_adx_update_map_ram(adx);
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tegra210_adx_set_in_byte_mask(adx);
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return 0;
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}
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static int tegra210_adx_set_audio_cif(struct snd_soc_dai *dai,
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int channels, int format,
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unsigned int reg)
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{
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struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
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struct tegra210_xbar_cif_conf cif_conf;
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int audio_bits;
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memset(&cif_conf, 0, sizeof(struct tegra210_xbar_cif_conf));
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if (channels < 1 || channels > 16)
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return -EINVAL;
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switch (format) {
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case SNDRV_PCM_FORMAT_S8:
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audio_bits = TEGRA210_AUDIOCIF_BITS_8;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_24;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA210_AUDIOCIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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cif_conf.audio_channels = channels;
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cif_conf.client_channels = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra210_xbar_set_cif(adx->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_adx_out_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
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int channels;
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if (adx->output_channels[dai->id] > 0)
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channels = adx->output_channels[dai->id];
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else
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channels = params_channels(params);
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return tegra210_adx_set_audio_cif(dai, channels, params_format(params),
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TEGRA210_ADX_AXBAR_TX1_CIF_CTRL +
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(dai->id * TEGRA210_ADX_AUDIOCIF_CH_STRIDE));
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}
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static int tegra210_adx_out_trigger(struct snd_pcm_substream *substream,
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int cmd,
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struct snd_soc_dai *dai)
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{
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struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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case SNDRV_PCM_TRIGGER_RESUME:
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tegra210_adx_enable_outstream(adx, dai->id);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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tegra210_adx_disable_outstream(adx, dai->id);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int tegra210_adx_in_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
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int channels;
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if (tegra_platform_is_unit_fpga() || tegra_platform_is_fpga()) {
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/* update the map ram */
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tegra210_adx_update_map_ram(adx);
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tegra210_adx_set_in_byte_mask(adx);
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}
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if (adx->input_channels > 0)
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channels = adx->input_channels;
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else
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channels = params_channels(params);
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return tegra210_adx_set_audio_cif(dai, channels, params_format(params),
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TEGRA210_ADX_AXBAR_RX_CIF_CTRL);
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}
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static int tegra210_adx_set_channel_map(struct snd_soc_dai *dai,
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unsigned int tx_num, unsigned int *tx_slot,
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unsigned int rx_num, unsigned int *rx_slot)
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{
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struct device *dev = dai->dev;
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struct tegra210_adx *adx = snd_soc_dai_get_drvdata(dai);
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unsigned int out_stream_idx, out_ch_idx, out_byte_idx;
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int i;
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if ((rx_num < 1) || (rx_num > 64)) {
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dev_err(dev, "Doesn't support %d rx_num, need to be 1 to 64\n",
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rx_num);
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return -EINVAL;
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}
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if (!rx_slot) {
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dev_err(dev, "rx_slot is NULL\n");
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return -EINVAL;
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}
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memset(adx->map, 0, sizeof(adx->map));
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memset(adx->byte_mask, 0, sizeof(adx->byte_mask));
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for (i = 0; i < rx_num; i++) {
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if (rx_slot[i] != 0) {
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/* getting mapping information */
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/* n-th output stream : 0 to 3 */
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out_stream_idx = (rx_slot[i] >> 16) & 0x3;
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/* n-th audio channel of output stream : 1 to 16 */
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out_ch_idx = (rx_slot[i] >> 8) & 0x1f;
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/* n-th byte of audio channel : 0 to 3 */
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out_byte_idx = rx_slot[i] & 0x3;
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tegra210_adx_set_map_table(adx, i, out_stream_idx,
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out_ch_idx - 1,
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out_byte_idx);
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/* making byte_mask */
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if (i > 31)
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adx->byte_mask[1] |= (1 << (i - 32));
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else
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adx->byte_mask[0] |= (1 << i);
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}
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}
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return 0;
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}
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static int tegra210_adx_get_byte_map(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra210_adx *adx = snd_soc_codec_get_drvdata(codec);
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struct soc_mixer_control *mc;
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unsigned char *bytes_map = (unsigned char *)&adx->map;
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int enabled;
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mc = (struct soc_mixer_control *)kcontrol->private_value;
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enabled = adx->byte_mask[mc->reg / 32] & (1 << (mc->reg % 32));
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if (enabled)
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ucontrol->value.integer.value[0] = bytes_map[mc->reg];
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else
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ucontrol->value.integer.value[0] = 256;
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return 0;
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}
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static int tegra210_adx_put_byte_map(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra210_adx *adx = snd_soc_codec_get_drvdata(codec);
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struct soc_mixer_control *mc;
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unsigned char *bytes_map = (unsigned char *)&adx->map;
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int value = ucontrol->value.integer.value[0];
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mc = (struct soc_mixer_control *)kcontrol->private_value;
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if (value >= 0 && value <= 255) {
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/* update byte map and enable slot */
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bytes_map[mc->reg] = value;
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adx->byte_mask[mc->reg / 32] |= (1 << (mc->reg % 32));
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} else {
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/* reset byte map and disable slot */
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bytes_map[mc->reg] = 0;
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adx->byte_mask[mc->reg / 32] &= ~(1 << (mc->reg % 32));
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}
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return 0;
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}
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static int tegra210_adx_get_in_channels(struct snd_kcontrol *kcontrol,
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
{
|
|
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
|
struct tegra210_adx *adx = snd_soc_codec_get_drvdata(codec);
|
|
|
|
ucontrol->value.integer.value[0] = adx->input_channels;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra210_adx_put_in_channels(struct snd_kcontrol *kcontrol,
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
{
|
|
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
|
struct tegra210_adx *adx = snd_soc_codec_get_drvdata(codec);
|
|
int value = ucontrol->value.integer.value[0];
|
|
|
|
if (value < 0 || value > 16)
|
|
return -EINVAL;
|
|
|
|
adx->input_channels = value;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra210_adx_get_out_channels(struct snd_kcontrol *kcontrol,
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
{
|
|
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
|
struct tegra210_adx *adx = snd_soc_codec_get_drvdata(codec);
|
|
struct soc_mixer_control *mc;
|
|
|
|
mc = (struct soc_mixer_control *)kcontrol->private_value;
|
|
|
|
ucontrol->value.integer.value[0] = adx->output_channels[mc->reg - 1];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra210_adx_put_out_channels(struct snd_kcontrol *kcontrol,
|
|
struct snd_ctl_elem_value *ucontrol)
|
|
{
|
|
struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
|
|
struct tegra210_adx *adx = snd_soc_codec_get_drvdata(codec);
|
|
struct soc_mixer_control *mc;
|
|
int value = ucontrol->value.integer.value[0];
|
|
|
|
mc = (struct soc_mixer_control *)kcontrol->private_value;
|
|
|
|
if (value < 0 || value > 16)
|
|
return -EINVAL;
|
|
|
|
adx->output_channels[mc->reg - 1] = value;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct snd_soc_dai_ops tegra210_adx_in_dai_ops = {
|
|
.hw_params = tegra210_adx_in_hw_params,
|
|
.set_channel_map = tegra210_adx_set_channel_map,
|
|
};
|
|
|
|
static struct snd_soc_dai_ops tegra210_adx_out_dai_ops = {
|
|
.hw_params = tegra210_adx_out_hw_params,
|
|
.trigger = tegra210_adx_out_trigger,
|
|
};
|
|
|
|
#define OUT_DAI(id) \
|
|
{ \
|
|
.name = "OUT" #id, \
|
|
.capture = { \
|
|
.stream_name = "OUT" #id " Transmit", \
|
|
.channels_min = 1, \
|
|
.channels_max = 16, \
|
|
.rates = SNDRV_PCM_RATE_8000_96000, \
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE, \
|
|
}, \
|
|
.ops = &tegra210_adx_out_dai_ops, \
|
|
}
|
|
|
|
#define IN_DAI(sname, dai_ops) \
|
|
{ \
|
|
.name = #sname, \
|
|
.playback = { \
|
|
.stream_name = #sname " Receive", \
|
|
.channels_min = 1, \
|
|
.channels_max = 16, \
|
|
.rates = SNDRV_PCM_RATE_8000_96000, \
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE, \
|
|
}, \
|
|
.ops = dai_ops, \
|
|
}
|
|
|
|
static struct snd_soc_dai_driver tegra210_adx_dais[] = {
|
|
OUT_DAI(1),
|
|
OUT_DAI(2),
|
|
OUT_DAI(3),
|
|
OUT_DAI(4),
|
|
IN_DAI(IN, &tegra210_adx_in_dai_ops),
|
|
};
|
|
|
|
static const struct snd_soc_dapm_widget tegra210_adx_widgets[] = {
|
|
SND_SOC_DAPM_AIF_IN_E("IN", NULL, 0, TEGRA210_ADX_ENABLE,
|
|
TEGRA210_ADX_ENABLE_SHIFT, 0,
|
|
tegra210_adx_stop, SND_SOC_DAPM_POST_PMD),
|
|
SND_SOC_DAPM_AIF_OUT("OUT1", NULL, 0, TEGRA210_ADX_CTRL, 0, 0),
|
|
SND_SOC_DAPM_AIF_OUT("OUT2", NULL, 0, TEGRA210_ADX_CTRL, 1, 0),
|
|
SND_SOC_DAPM_AIF_OUT("OUT3", NULL, 0, TEGRA210_ADX_CTRL, 2, 0),
|
|
SND_SOC_DAPM_AIF_OUT("OUT4", NULL, 0, TEGRA210_ADX_CTRL, 3, 0),
|
|
};
|
|
|
|
static const struct snd_soc_dapm_route tegra210_adx_routes[] = {
|
|
{ "IN", NULL, "IN Receive" },
|
|
{ "OUT1", NULL, "IN" },
|
|
{ "OUT2", NULL, "IN" },
|
|
{ "OUT3", NULL, "IN" },
|
|
{ "OUT4", NULL, "IN" },
|
|
{ "OUT1 Transmit", NULL, "OUT1" },
|
|
{ "OUT2 Transmit", NULL, "OUT2" },
|
|
{ "OUT3 Transmit", NULL, "OUT3" },
|
|
{ "OUT4 Transmit", NULL, "OUT4" },
|
|
};
|
|
|
|
#define TEGRA210_ADX_BYTE_MAP_CTRL(reg) \
|
|
SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \
|
|
tegra210_adx_get_byte_map, \
|
|
tegra210_adx_put_byte_map)
|
|
|
|
#define TEGRA210_ADX_OUTPUT_CHANNELS_CTRL(reg) \
|
|
SOC_SINGLE_EXT("Output" #reg " Channels", reg, 0, 16, 0, \
|
|
tegra210_adx_get_out_channels, \
|
|
tegra210_adx_put_out_channels)
|
|
|
|
#define TEGRA210_ADX_INPUT_CHANNELS_CTRL(reg) \
|
|
SOC_SINGLE_EXT("Input Channels", reg, 0, 16, 0, \
|
|
tegra210_adx_get_in_channels, \
|
|
tegra210_adx_put_in_channels)
|
|
|
|
static struct snd_kcontrol_new tegra210_adx_controls[] = {
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(0),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(1),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(2),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(3),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(4),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(5),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(6),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(7),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(8),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(9),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(10),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(11),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(12),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(13),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(14),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(15),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(16),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(17),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(18),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(19),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(20),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(21),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(22),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(23),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(24),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(25),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(26),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(27),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(28),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(29),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(30),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(31),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(32),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(33),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(34),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(35),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(36),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(37),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(38),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(39),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(40),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(41),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(42),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(43),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(44),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(45),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(46),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(47),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(48),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(49),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(50),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(51),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(52),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(53),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(54),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(55),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(56),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(57),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(58),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(59),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(60),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(61),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(62),
|
|
TEGRA210_ADX_BYTE_MAP_CTRL(63),
|
|
|
|
TEGRA210_ADX_OUTPUT_CHANNELS_CTRL(1),
|
|
TEGRA210_ADX_OUTPUT_CHANNELS_CTRL(2),
|
|
TEGRA210_ADX_OUTPUT_CHANNELS_CTRL(3),
|
|
TEGRA210_ADX_OUTPUT_CHANNELS_CTRL(4),
|
|
TEGRA210_ADX_INPUT_CHANNELS_CTRL(1),
|
|
};
|
|
|
|
static struct snd_soc_codec_driver tegra210_adx_codec = {
|
|
.idle_bias_off = 1,
|
|
.component_driver = {
|
|
.dapm_widgets = tegra210_adx_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(tegra210_adx_widgets),
|
|
.dapm_routes = tegra210_adx_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(tegra210_adx_routes),
|
|
.controls = tegra210_adx_controls,
|
|
.num_controls = ARRAY_SIZE(tegra210_adx_controls),
|
|
},
|
|
};
|
|
|
|
static bool tegra210_adx_wr_reg(struct device *dev,
|
|
unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case TEGRA210_ADX_AXBAR_TX_INT_MASK:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_SET:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_CLEAR:
|
|
case TEGRA210_ADX_AXBAR_TX1_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_TX2_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_TX3_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_TX4_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_MASK:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_SET:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_CLEAR:
|
|
case TEGRA210_ADX_AXBAR_RX_CIF_CTRL:
|
|
case TEGRA210_ADX_ENABLE:
|
|
case TEGRA210_ADX_SOFT_RESET:
|
|
case TEGRA210_ADX_CG:
|
|
case TEGRA210_ADX_CTRL:
|
|
case TEGRA210_ADX_IN_BYTE_EN0:
|
|
case TEGRA210_ADX_IN_BYTE_EN1:
|
|
case TEGRA210_ADX_CYA:
|
|
case TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL:
|
|
case TEGRA210_ADX_AHUBRAMCTL_ADX_DATA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
};
|
|
}
|
|
|
|
static bool tegra210_adx_rd_reg(struct device *dev,
|
|
unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case TEGRA210_ADX_AXBAR_RX_STATUS:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_STATUS:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_MASK:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_SET:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_CLEAR:
|
|
case TEGRA210_ADX_AXBAR_RX_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_TX_STATUS:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_STATUS:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_MASK:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_SET:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_CLEAR:
|
|
case TEGRA210_ADX_AXBAR_TX1_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_TX2_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_TX3_CIF_CTRL:
|
|
case TEGRA210_ADX_AXBAR_TX4_CIF_CTRL:
|
|
case TEGRA210_ADX_ENABLE:
|
|
case TEGRA210_ADX_SOFT_RESET:
|
|
case TEGRA210_ADX_CG:
|
|
case TEGRA210_ADX_STATUS:
|
|
case TEGRA210_ADX_INT_STATUS:
|
|
case TEGRA210_ADX_CTRL:
|
|
case TEGRA210_ADX_IN_BYTE_EN0:
|
|
case TEGRA210_ADX_IN_BYTE_EN1:
|
|
case TEGRA210_ADX_CYA:
|
|
case TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL:
|
|
case TEGRA210_ADX_AHUBRAMCTL_ADX_DATA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
};
|
|
}
|
|
|
|
static bool tegra210_adx_volatile_reg(struct device *dev,
|
|
unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case TEGRA210_ADX_AXBAR_RX_STATUS:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_STATUS:
|
|
case TEGRA210_ADX_AXBAR_RX_INT_SET:
|
|
case TEGRA210_ADX_AXBAR_TX_STATUS:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_STATUS:
|
|
case TEGRA210_ADX_AXBAR_TX_INT_SET:
|
|
case TEGRA210_ADX_SOFT_RESET:
|
|
case TEGRA210_ADX_STATUS:
|
|
case TEGRA210_ADX_INT_STATUS:
|
|
case TEGRA210_ADX_AHUBRAMCTL_ADX_CTRL:
|
|
case TEGRA210_ADX_AHUBRAMCTL_ADX_DATA:
|
|
return true;
|
|
default:
|
|
break;
|
|
};
|
|
|
|
return false;
|
|
}
|
|
|
|
static const struct regmap_config tegra210_adx_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = TEGRA210_ADX_AHUBRAMCTL_ADX_DATA,
|
|
.writeable_reg = tegra210_adx_wr_reg,
|
|
.readable_reg = tegra210_adx_rd_reg,
|
|
.volatile_reg = tegra210_adx_volatile_reg,
|
|
.reg_defaults = tegra210_adx_reg_defaults,
|
|
.num_reg_defaults = ARRAY_SIZE(tegra210_adx_reg_defaults),
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
static const struct of_device_id tegra210_adx_of_match[] = {
|
|
{ .compatible = "nvidia,tegra210-adx" },
|
|
{},
|
|
};
|
|
|
|
static int tegra210_adx_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra210_adx *adx;
|
|
struct resource *mem;
|
|
void __iomem *regs;
|
|
int ret = 0;
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_device(tegra210_adx_of_match, &pdev->dev);
|
|
if (!match) {
|
|
dev_err(&pdev->dev, "Error: No device match found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
adx = devm_kzalloc(&pdev->dev, sizeof(*adx), GFP_KERNEL);
|
|
if (!adx)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(&pdev->dev, adx);
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
regs = devm_ioremap_resource(&pdev->dev, mem);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
adx->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
|
&tegra210_adx_regmap_config);
|
|
if (IS_ERR(adx->regmap)) {
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
|
return PTR_ERR(adx->regmap);
|
|
}
|
|
regcache_cache_only(adx->regmap, true);
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node,
|
|
"nvidia,ahub-adx-id",
|
|
&pdev->dev.id);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Missing property nvidia,ahub-adx-id\n");
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
ret = snd_soc_register_codec(&pdev->dev, &tegra210_adx_codec,
|
|
tegra210_adx_dais,
|
|
ARRAY_SIZE(tegra210_adx_dais));
|
|
if (ret != 0) {
|
|
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
|
pm_runtime_disable(&pdev->dev);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra210_adx_platform_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra210_adx_runtime_suspend(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra210_adx_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra210_adx_runtime_suspend,
|
|
tegra210_adx_runtime_resume, NULL)
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra210_adx_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra210_adx_of_match,
|
|
.pm = &tegra210_adx_pm_ops,
|
|
},
|
|
.probe = tegra210_adx_platform_probe,
|
|
.remove = tegra210_adx_platform_remove,
|
|
};
|
|
module_platform_driver(tegra210_adx_driver);
|
|
|
|
MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra210 ADX ASoC driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra210_adx_of_match);
|