forked from rrcarlosr/Jetpack
660 lines
19 KiB
C
660 lines
19 KiB
C
/*
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* dsi.h: Functions implementing tegra dsi interface.
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*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_DSI_H__
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#define __DRIVERS_VIDEO_TEGRA_DC_DSI_H__
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#define BOARD_P1761 0x06E1
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#define MAX_XRES 4096
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#include "dc_priv_defs.h"
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#include <linux/reset.h>
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#ifdef CONFIG_TEGRA_SYS_EDP
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#include <soc/tegra/sysedp.h>
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#endif
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#include "dsi_padctrl.h"
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#include "dc_priv.h"
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#include "hpd.h"
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#define DSI_PADCTRL_INDEX 4
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enum {
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PAD_AB_ACTIVE,
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PAD_AB_INACTIVE,
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PAD_CD_ACTIVE,
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PAD_CD_INACTIVE,
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PAD_INVALID,
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};
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/* Defines the DSI phy timing parameters */
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struct dsi_phy_timing_inclk {
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unsigned t_hsdexit;
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unsigned t_hstrail;
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unsigned t_hsprepare;
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unsigned t_datzero;
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unsigned t_clktrail;
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unsigned t_clkpost;
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unsigned t_clkzero;
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unsigned t_tlpx;
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unsigned t_clkpre;
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unsigned t_clkprepare;
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unsigned t_wakeup;
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unsigned t_taget;
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unsigned t_tasure;
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unsigned t_tago;
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};
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struct dsi_status {
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unsigned init:2;
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unsigned lphs:2;
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unsigned vtype:2;
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unsigned driven:2;
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unsigned clk_out:2;
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unsigned clk_mode:2;
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unsigned clk_burst:2;
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unsigned lp_op:2;
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unsigned dc_stream:1;
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};
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struct dsi_regs {
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int init_seq_data_15; /* convert into an array if at all needed */
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int slew_impedance[4];
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int preemphasis;
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int bias;
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int ganged_mode_control;
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int ganged_mode_start;
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int ganged_mode_size;
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int dsi_dsc_control;
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};
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struct tegra_dc_dsi_data {
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struct tegra_dc *dc;
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void __iomem **base;
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void __iomem *pad_control_base;
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struct clk *dc_clk;
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struct clk **dsi_clk;
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struct clk *dsi_fixed_clk;
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struct clk **dsi_lp_clk;
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struct clk *dsc_clk;
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struct reset_control **dsi_reset;
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bool clk_ref;
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struct mutex lock;
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int max_instances;
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struct tegra_dsi_out_ops *out_ops;
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void *out_data;
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/* data from board info */
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struct tegra_dsi_out info;
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struct tegra_hpd_data hpd_data;
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struct dsi_status status;
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struct dsi_phy_timing_inclk phy_timing;
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bool ulpm;
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bool enabled;
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bool host_suspended;
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struct mutex host_lock;
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struct delayed_work idle_work;
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unsigned long idle_delay;
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atomic_t host_ref;
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u8 driven_mode;
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u8 controller_index;
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u8 pixel_scaler_mul;
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u8 pixel_scaler_div;
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struct tegra_dc_shift_clk_div default_shift_clk_div;
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u32 default_pixel_clk_khz;
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u32 default_hs_clk_khz;
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struct tegra_dc_shift_clk_div shift_clk_div;
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u32 target_hs_clk_khz;
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u32 target_lp_clk_khz;
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u32 syncpt_id;
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u32 syncpt_val;
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u32 current_bit_clk_ps;
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u32 current_dsi_clk_khz;
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struct regulator *avdd_dsi_csi;
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u32 dsi_control_val;
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u32 device_shutdown;
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struct sysedp_consumer *sysedpc;
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struct pinctrl *dsi_io_pad_pinctrl;
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struct pinctrl_state *dpd_enable[4];
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struct tegra_dsi_padctrl *pad_ctrl;
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struct tegra_prod *prod_list;
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struct pinctrl *pin;
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struct pinctrl_state *pin_state[PAD_INVALID];
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const struct dsi_regs *regs;
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};
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/* Max number of data lanes supported */
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#define MAX_DSI_DATA_LANES 8
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/* Default Peripheral reset timeout */
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#define DSI_PR_TO_VALUE 0x2000
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/* DCS commands for command mode */
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#define DSI_ENTER_PARTIAL_MODE 0x12
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#define DSI_SET_PIXEL_FORMAT 0x3A
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#define DSI_AREA_COLOR_MODE 0x4C
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#define DSI_SET_PARTIAL_AREA 0x30
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#define DSI_SET_PAGE_ADDRESS 0x2B
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#define DSI_SET_ADDRESS_MODE 0x36
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#define DSI_SET_COLUMN_ADDRESS 0x2A
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#define DSI_WRITE_MEMORY_START 0x2C
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#define DSI_WRITE_MEMORY_CONTINUE 0x3C
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#define DSI_MAX_COMMAND_DELAY_USEC 250000
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#define DSI_COMMAND_DELAY_STEPS_USEC 10
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/* Trigger message */
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#define DSI_ESCAPE_CMD 0x87
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#define DSI_ACK_NO_ERR 0x84
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/* DSI return packet types */
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#define GEN_LONG_RD_RES 0x1A
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#define DCS_LONG_RD_RES 0x1C
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#define GEN_1_BYTE_SHORT_RD_RES 0x11
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#define DCS_1_BYTE_SHORT_RD_RES 0x21
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#define GEN_2_BYTE_SHORT_RD_RES 0x12
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#define DCS_2_BYTE_SHORT_RD_RES 0x22
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#define ACK_ERR_RES 0x02
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/* End of Transmit command for HS mode */
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#define DSI_CMD_HS_EOT_PACKAGE 0x000F0F08
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/* Delay required after issuing the trigger*/
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#define DSI_COMMAND_COMPLETION_DELAY_USEC 5
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#define DSI_DELAY_FOR_READ_FIFO 5
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/* Dsi virtual channel bit position, refer to the DSI specs */
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#define DSI_VIR_CHANNEL_BIT_POSITION 6
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/* DSI packet commands from Host to peripherals */
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enum {
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dsi_command_v_sync_start = 0x01,
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dsi_command_v_sync_end = 0x11,
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dsi_command_h_sync_start = 0x21,
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dsi_command_h_sync_end = 0x31,
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dsi_command_end_of_transaction = 0x08,
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dsi_command_blanking = 0x19,
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dsi_command_null_packet = 0x09,
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dsi_command_h_active_length_16bpp = 0x0E,
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dsi_command_h_active_length_18bpp = 0x1E,
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dsi_command_h_active_length_18bpp_np = 0x2E,
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dsi_command_h_active_length_24bpp = 0x3E,
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dsi_command_h_sync_active = dsi_command_blanking,
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dsi_command_h_back_porch = dsi_command_blanking,
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dsi_command_h_front_porch = dsi_command_blanking,
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dsi_command_writ_no_param = 0x05,
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dsi_command_long_write = 0x39,
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dsi_command_max_return_pkt_size = 0x37,
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dsi_command_generic_read_request_with_2_param = 0x24,
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dsi_command_dcs_read_with_no_params = 0x06,
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};
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/* Maximum polling time for reading the dsi status register */
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#define DSI_STATUS_POLLING_DURATION_USEC 100000
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#define DSI_STATUS_POLLING_DELAY_USEC 100
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/*
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* Horizontal Sync Blank Packet Over head
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* DSI_overhead = size_of(HS packet header)
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* + size_of(BLANK packet header) + size_of(checksum)
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* DSI_overhead = 4 + 4 + 2 = 10
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*/
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#define DSI_HSYNC_BLNK_PKT_OVERHEAD 10
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/*
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* Horizontal Front Porch Packet Overhead
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* DSI_overhead = size_of(checksum)
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* + size_of(BLANK packet header) + size_of(checksum)
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* DSI_overhead = 2 + 4 + 2 = 8
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*/
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#define DSI_HFRONT_PORCH_PKT_OVERHEAD 8
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/*
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* Horizontal Back Porch Packet
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* DSI_overhead = size_of(HE packet header)
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* + size_of(BLANK packet header) + size_of(checksum)
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* + size_of(RGB packet header)
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* DSI_overhead = 4 + 4 + 2 + 4 = 14
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*/
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#define DSI_HBACK_PORCH_PKT_OVERHEAD 14
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/*
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* Compressed packet overhead in video mode
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* DSI overhead = size_of(packet header) + size_of(checksum)
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* DSI_overhead = 4 + 2 = 6
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*/
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#define DSI_VIDEO_MODE_COMP_PKT_OVERHEAD 6
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/*
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* Compressed packet overhead in cmd mode
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* DSI overhead = size_of(packet header) + size_of(checksum) +
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* + size_of(CMD_BYTE)
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* DSI_overhead = 4 + 2 + 1 = 7
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*/
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#define DSI_CMD_MODE_COMP_PKT_OVERHEAD 7
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/* Checksum overhead = 2 bytes */
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#define DSI_CHECKSUM_OVERHEAD 2
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/* DSI blank pkt overhead
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* DSI overhead = size_of(BLANK packet header) + size_of(checksum)
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* DSI_overhead = 4 + 2 = 6
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*/
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#define DSI_BLNK_PKT_OVERHEAD 6
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/* Additional Hs TX timeout margin */
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#define DSI_HTX_TO_MARGIN 720
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#define DSI_CYCLE_COUNTER_VALUE 512
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#define DSI_LRXH_TO_VALUE 0x2000
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/* Turn around timeout terminal count */
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#define DSI_TA_TO_VALUE 0x2000
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/* Turn around timeout tally */
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#define DSI_TA_TALLY_VALUE 0x0
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/* LP Rx timeout tally */
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#define DSI_LRXH_TALLY_VALUE 0x0
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/* HS Tx Timeout tally */
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#define DSI_HTX_TALLY_VALUE 0x0
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/* DSI Power control settle time 10 micro seconds */
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#define DSI_POWER_CONTROL_SETTLE_TIME_US 10
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#define DSI_HOST_FIFO_DEPTH 64
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#define DSI_VIDEO_FIFO_DEPTH 480
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#define DSI_READ_FIFO_DEPTH (32 << 2)
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#define NUMOF_BIT_PER_BYTE 8
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#define DEFAULT_LP_CMD_MODE_CLK_KHZ 10000
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#define DEFAULT_MAX_DSI_PHY_CLK_KHZ (500*1000)
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#define DEFAULT_PANEL_RESET_TIMEOUT 2
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#define DEFAULT_PANEL_BUFFER_BYTE 512
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/*
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* TODO: are DSI_HOST_DSI_CONTROL_CRC_RESET(RESET_CRC) and
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* DSI_HOST_DSI_CONTROL_HOST_TX_TRIG_SRC(IMMEDIATE) required for everyone?
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*/
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#define HOST_DSI_CTRL_COMMON \
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(DSI_HOST_DSI_CONTROL_PHY_CLK_DIV(DSI_PHY_CLK_DIV1) | \
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DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL) | \
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DSI_HOST_DSI_CONTROL_PERIPH_RESET(TEGRA_DSI_DISABLE) | \
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DSI_HOST_DSI_CONTROL_RAW_DATA(TEGRA_DSI_DISABLE) | \
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DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_DISABLE) | \
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DSI_HOST_DSI_CONTROL_PKT_BTA(TEGRA_DSI_DISABLE) | \
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DSI_HOST_DSI_CONTROL_CS_ENABLE(TEGRA_DSI_ENABLE) | \
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DSI_HOST_DSI_CONTROL_ECC_ENABLE(TEGRA_DSI_ENABLE) | \
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DSI_HOST_DSI_CONTROL_PKT_WR_FIFO_SEL(HOST_ONLY))
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#define HOST_DSI_CTRL_HOST_DRIVEN \
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(DSI_HOST_DSI_CONTROL_CRC_RESET(RESET_CRC) | \
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DSI_HOST_DSI_CONTROL_HOST_TX_TRIG_SRC(IMMEDIATE))
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#define HOST_DSI_CTRL_DC_DRIVEN 0
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#define DSI_CTRL_HOST_DRIVEN (DSI_CONTROL_VID_ENABLE(TEGRA_DSI_DISABLE) | \
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DSI_CONTROL_HOST_ENABLE(TEGRA_DSI_ENABLE))
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#define DSI_CTRL_DC_DRIVEN (DSI_CONTROL_VID_TX_TRIG_SRC(SOL) | \
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DSI_CONTROL_VID_ENABLE(TEGRA_DSI_ENABLE) | \
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DSI_CONTROL_HOST_ENABLE(TEGRA_DSI_DISABLE))
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#define DSI_CTRL_CMD_MODE (DSI_CONTROL_VID_DCS_ENABLE(TEGRA_DSI_ENABLE))
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#define DSI_CTRL_VIDEO_MODE (DSI_CONTROL_VID_DCS_ENABLE(TEGRA_DSI_DISABLE))
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/* Mipi v1.00.00 phy timing range */
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#define NOT_DEFINED -1
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#define MIPI_T_HSEXIT_PS_MIN (100 * 1000)
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#define MIPI_T_HSEXIT_PS_MAX NOT_DEFINED
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#define MIPI_T_HSTRAIL_PS_MIN(clk_ps) max((8 * (clk_ps)), \
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(60 * 1000 + 4 * (clk_ps)))
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#define MIPI_T_HSTRAIL_PS_MAX NOT_DEFINED
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#define MIPI_T_HSZERO_PS_MIN NOT_DEFINED
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#define MIPI_T_HSZERO_PS_MAX NOT_DEFINED
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#define MIPI_T_HSPREPARE_PS_MIN(clk_ps) (40 * 1000 + 4 * (clk_ps))
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#define MIPI_T_HSPREPARE_PS_MAX(clk_ps) (85 * 1000 + 6 * (clk_ps))
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#define MIPI_T_CLKTRAIL_PS_MIN (60 * 1000)
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#define MIPI_T_CLKTRAIL_PS_MAX NOT_DEFINED
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#define MIPI_T_CLKPOST_PS_MIN(clk_ps) (60 * 1000 + 52 * (clk_ps))
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#define MIPI_T_CLKPOST_PS_MAX NOT_DEFINED
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#define MIPI_T_CLKZERO_PS_MIN NOT_DEFINED
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#define MIPI_T_CLKZERO_PS_MAX NOT_DEFINED
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#define MIPI_T_TLPX_PS_MIN (50 * 1000)
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#define MIPI_T_TLPX_PS_MAX NOT_DEFINED
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#define MIPI_T_CLKPREPARE_PS_MIN (38 * 1000)
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#define MIPI_T_CLKPREPARE_PS_MAX (95 * 1000)
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#define MIPI_T_CLKPRE_PS_MIN (8 * 1000)
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#define MIPI_T_CLKPRE_PS_MAX NOT_DEFINED
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#define MIPI_T_WAKEUP_PS_MIN (1 * 1000)
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#define MIPI_T_WAKEUP_PS_MAX NOT_DEFINED
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#define MIPI_T_TASURE_PS_MIN(tlpx_ps) (tlpx_ps)
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#define MIPI_T_TASURE_PS_MAX(tlpx_ps) (2 * (tlpx_ps))
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#define MIPI_T_HSPREPARE_ADD_HSZERO_PS_MIN(clk_ps) \
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(145 * 1000 + 10 * (clk_ps))
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#define MIPI_T_HSPREPARE_ADD_HSZERO_PS_MAX NOT_DEFINED
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#define MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MIN (300 * 1000)
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#define MIPI_T_CLKPREPARE_ADD_CLKZERO_PS_MAX NOT_DEFINED
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#define DSI_TBYTE(clk_ps) ((clk_ps) * (BITS_PER_BYTE))
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#define DSI_CONVERT_T_PHY_PS_TO_T_PHY(t_phy_ps, clk_ps, hw_inc) \
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((int)((DIV_ROUND_CLOSEST((t_phy_ps), \
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(DSI_TBYTE(clk_ps)))) - (hw_inc)))
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#define DSI_CONVERT_T_PHY_TO_T_PHY_PS(t_phy, clk_ps, hw_inc) \
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(((t_phy) + (hw_inc)) * (DSI_TBYTE(clk_ps)))
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/* Default phy timing in ns */
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#define T_HSEXIT_PS_DEFAULT (120 * 1000)
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#define T_HSTRAIL_PS_DEFAULT(clk_ps) \
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max((8 * (clk_ps)), \
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(60 * 1000 + 4 * (clk_ps)))
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#define T_DATZERO_PS_DEFAULT(clk_ps) (145 * 1000 + 5 * (clk_ps))
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#define T_HSPREPARE_PS_DEFAULT(clk_ps) (65 * 1000 + 5 * (clk_ps))
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#define T_CLKTRAIL_PS_DEFAULT (80 * 1000)
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#define T_CLKPOST_PS_DEFAULT(clk_ps) (70 * 1000 + 52 * (clk_ps))
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#define T_CLKZERO_PS_DEFAULT (260 * 1000)
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#define T_TLPX_PS_DEFAULT (60 * 1000)
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#define T_CLKPREPARE_PS_DEFAULT (65 * 1000)
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#define T_TAGO_PS_DEFAULT (4 * (T_TLPX_PS_DEFAULT))
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#define T_TASURE_PS_DEFAULT (2 * (T_TLPX_PS_DEFAULT))
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#define T_TAGET_PS_DEFAULT (5 * (T_TLPX_PS_DEFAULT))
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/* HW increment to phy register values */
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#define T_HSEXIT_HW_INC 1
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#define T_HSTRAIL_HW_INC 0
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#define T_DATZERO_HW_INC 3
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#define T_HSPREPARE_HW_INC 1
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#define T_CLKTRAIL_HW_INC 1
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#define T_CLKPOST_HW_INC 1
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#define T_CLKZERO_HW_INC 1
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#define T_TLPX_HW_INC 1
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#define T_CLKPREPARE_HW_INC 1
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#define T_TAGO_HW_INC 1
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#define T_TASURE_HW_INC 1
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#define T_TAGET_HW_INC 1
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#define T_CLKPRE_HW_INC 1
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#define T_WAKEUP_HW_INC 1
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/* Default phy timing reg values */
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#define T_HSEXIT_DEFAULT(clk_ps) \
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(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
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T_HSEXIT_PS_DEFAULT, clk_ps, T_HSEXIT_HW_INC))
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#define T_HSTRAIL_DEFAULT(clk_ps) \
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(3 + (DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
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T_HSTRAIL_PS_DEFAULT(clk_ps), clk_ps, T_HSTRAIL_HW_INC)))
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#define T_DATZERO_DEFAULT(clk_ps) \
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(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
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T_DATZERO_PS_DEFAULT(clk_ps), clk_ps, T_DATZERO_HW_INC))
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#define T_HSPREPARE_DEFAULT(clk_ps) \
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(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
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T_HSPREPARE_PS_DEFAULT(clk_ps), clk_ps, T_HSPREPARE_HW_INC))
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#define T_CLKTRAIL_DEFAULT(clk_ps) \
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(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
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T_CLKTRAIL_PS_DEFAULT, clk_ps, T_CLKTRAIL_HW_INC))
|
|
|
|
#define T_CLKPOST_DEFAULT(clk_ps) \
|
|
(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
|
|
T_CLKPOST_PS_DEFAULT(clk_ps), clk_ps, T_CLKPOST_HW_INC))
|
|
|
|
#define T_CLKZERO_DEFAULT(clk_ps) \
|
|
(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
|
|
T_CLKZERO_PS_DEFAULT, clk_ps, T_CLKZERO_HW_INC))
|
|
|
|
#define T_TLPX_DEFAULT(clk_ps) \
|
|
(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
|
|
T_TLPX_PS_DEFAULT, clk_ps, T_TLPX_HW_INC))
|
|
|
|
#define T_CLKPREPARE_DEFAULT(clk_ps) \
|
|
(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
|
|
T_CLKPREPARE_PS_DEFAULT, clk_ps, T_CLKPREPARE_HW_INC))
|
|
|
|
#define T_CLKPRE_DEFAULT 0x1
|
|
#define T_WAKEUP_DEFAULT 0xff
|
|
|
|
#define T_TAGO_DEFAULT(clk_ps) \
|
|
(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
|
|
T_TAGO_PS_DEFAULT, clk_ps, T_TAGO_HW_INC))
|
|
|
|
#define T_TASURE_DEFAULT(clk_ps) \
|
|
(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
|
|
T_TASURE_PS_DEFAULT, clk_ps, T_TASURE_HW_INC))
|
|
|
|
#define T_TAGET_DEFAULT(clk_ps) \
|
|
(DSI_CONVERT_T_PHY_PS_TO_T_PHY( \
|
|
T_TAGET_PS_DEFAULT, clk_ps, T_TAGET_HW_INC))
|
|
|
|
static inline u32 tegra_dc_get_dsi_base(void)
|
|
{
|
|
if (tegra_dc_is_nvdisplay())
|
|
return 0x15300000;
|
|
else
|
|
return 0x54300000;
|
|
}
|
|
|
|
static inline u32 tegra_dc_get_dsi_instance_0(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 tegra_dc_get_dsi_instance_1(void)
|
|
{
|
|
if (tegra_dc_is_nvdisplay())
|
|
/* T186 has 4 controllers. DSI-A and DSI-C are the main
|
|
* controllers needed for ganged mode.
|
|
*/
|
|
return 2;
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
#define TEGRA_DSI_SIZE SZ_256K
|
|
|
|
#define TEGRA_VIC_BASE 0x54340000
|
|
#define TEGRA_VIC_SIZE SZ_256K
|
|
|
|
static inline u32 tegra_dc_get_dsib_base(void)
|
|
{
|
|
if (tegra_dc_is_nvdisplay())
|
|
return 0x15400000;
|
|
else
|
|
return 0x54400000;
|
|
}
|
|
|
|
#define TEGRA_DSIB_SIZE SZ_256K
|
|
|
|
/* Used only on Nvdisplay */
|
|
#define TEGRA_DSIC_BASE 0x15900000
|
|
#define TEGRA_DSIC_SIZE SZ_256K
|
|
#define TEGRA_DSID_BASE 0x15940000
|
|
#define TEGRA_DSID_SIZE SZ_256K
|
|
#define TEGRA_DSI_PADCTL_BASE 0x15880000
|
|
#define TEGRA_DSI_PADCTL_SIZE SZ_64K
|
|
|
|
struct tegra_dsi_out_ops {
|
|
/* initialize output. dsi clocks are not on at this point */
|
|
int (*init)(struct tegra_dc_dsi_data *);
|
|
/* destroy output. dsi clocks are not on at this point */
|
|
void (*destroy)(struct tegra_dc_dsi_data *);
|
|
/* enable output. dsi clocks are on at this point */
|
|
void (*enable)(struct tegra_dc_dsi_data *);
|
|
/* disable output. dsi clocks are on at this point */
|
|
void (*disable)(struct tegra_dc_dsi_data *dc);
|
|
/* suspend output. dsi clocks are on at this point */
|
|
void (*suspend)(struct tegra_dc_dsi_data *);
|
|
/* resume output. dsi clocks are on at this point */
|
|
void (*resume)(struct tegra_dc_dsi_data *);
|
|
/* output postpoweron, called at the end of dc out_ops postpoweron.
|
|
* usually used for bridge devices.
|
|
* dsi clocks and video stream are on at this point */
|
|
void (*postpoweron)(struct tegra_dc_dsi_data *);
|
|
};
|
|
|
|
#if defined(CONFIG_TEGRA_DSI2EDP_TC358767) || \
|
|
defined(CONFIG_TEGRA_DSI2EDP_SN65DSI86)
|
|
extern struct tegra_dsi_out_ops tegra_dsi2edp_ops;
|
|
#else
|
|
#define tegra_dsi2edp_ops (*(struct tegra_dsi_out_ops *)NULL)
|
|
#endif
|
|
|
|
#if defined(CONFIG_TEGRA_DSI2LVDS_SN65DSI85)
|
|
extern struct tegra_dsi_out_ops tegra_dsi2lvds_ops;
|
|
#else
|
|
#define tegra_dsi2lvds_ops (*(struct tegra_dsi_out_ops *)NULL)
|
|
#endif
|
|
|
|
#if defined(CONFIG_TEGRA_LVDS2FPDL_DS90UB947)
|
|
extern bool ds90ub947_lvds2fpdlink3_detect(struct tegra_dc *dc);
|
|
#endif
|
|
|
|
struct sanity_status {
|
|
u32 sot_error:1;
|
|
u32 sot_sync_error:1;
|
|
u32 eot_sync_error:1;
|
|
u32 escape_mode_entry_comand_error:1;
|
|
u32 low_power_transmit_sync_error:1;
|
|
u32 hs_receive_timeout_error:1;
|
|
u32 false_control_error:1;
|
|
u32 reserved1:1;
|
|
u32 ecc_error_single_bit:1;
|
|
u32 ecc_error_multi_bit:1;
|
|
u32 checksum_error:1;
|
|
u32 dsi_data_type_not_recognized:1;
|
|
u32 dsi_vc_id_invalid:1;
|
|
u32 dsi_protocol_violation:1;
|
|
u32 reserved2:1;
|
|
u32 reserved3:1;
|
|
};
|
|
|
|
static inline u32 tegra_dc_get_max_dsi_instance(void)
|
|
{
|
|
if (tegra_dc_is_nvdisplay())
|
|
return 4;
|
|
else
|
|
return 2;
|
|
}
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi);
|
|
void tegra_dsi_csi_test_init(struct tegra_dc_dsi_data *dsi);
|
|
#endif
|
|
void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi);
|
|
void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi);
|
|
unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
|
|
u32 reg, int index);
|
|
unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg);
|
|
unsigned long tegra_dsi_pad_control_readl(struct tegra_dc_dsi_data *dsi,
|
|
u32 reg);
|
|
void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
|
|
u32 val, u32 reg, int index);
|
|
void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg);
|
|
void tegra_dsi_pad_control_writel(struct tegra_dc_dsi_data *dsi,
|
|
u32 val, u32 reg);
|
|
int tegra_dsi_read_data(struct tegra_dc *dc,
|
|
struct tegra_dc_dsi_data *dsi,
|
|
u16 max_ret_payload_size,
|
|
u8 panel_reg_addr, u8 *read_data);
|
|
int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
|
|
struct tegra_dc_dsi_data *dsi,
|
|
struct sanity_status *san);
|
|
bool tegra_dsi_enable_read_debug(struct tegra_dc_dsi_data *dsi);
|
|
bool tegra_dsi_disable_read_debug(struct tegra_dc_dsi_data *dsi);
|
|
int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi,
|
|
struct tegra_dsi_cmd *cmd);
|
|
void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi);
|
|
int tegra_dsi_write_data(struct tegra_dc *dc,
|
|
struct tegra_dc_dsi_data *dsi,
|
|
struct tegra_dsi_cmd *cmd, u8 delay_ms);
|
|
int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
|
|
struct tegra_dc_dsi_data *dsi,
|
|
struct tegra_dsi_cmd *cmd,
|
|
u32 n_cmd);
|
|
|
|
void tegra_dsi_init_clock_param(struct tegra_dc *dc);
|
|
|
|
struct dsi_status *tegra_dsi_prepare_host_transmission(
|
|
struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi, u8 lp_op);
|
|
int tegra_dsi_restore_state(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi,
|
|
struct dsi_status *init_status);
|
|
|
|
static inline void *tegra_dsi_get_outdata(struct tegra_dc_dsi_data *dsi)
|
|
{
|
|
return dsi->out_data;
|
|
}
|
|
|
|
static inline void tegra_dsi_set_outdata(struct tegra_dc_dsi_data *dsi,
|
|
void *data)
|
|
{
|
|
dsi->out_data = data;
|
|
}
|
|
|
|
static inline bool is_simple_dsi(struct tegra_dsi_out *dsi_out)
|
|
{
|
|
return !(dsi_out->ganged_type ||
|
|
dsi_out->dsi_csi_loopback ||
|
|
dsi_out->split_link_type);
|
|
}
|
|
|
|
|
|
static inline int tegra_dsi_get_max_active_instances_num(
|
|
struct tegra_dsi_out *dsi_out)
|
|
{
|
|
int ret = 0, max_instances = 0;
|
|
bool simple_dsi = 0;
|
|
|
|
max_instances = tegra_dc_get_max_dsi_instance();
|
|
simple_dsi = is_simple_dsi(dsi_out);
|
|
|
|
if (tegra_dc_is_nvdisplay())
|
|
ret = simple_dsi ? 2 : max_instances;
|
|
else
|
|
ret = simple_dsi ? 1 : max_instances;
|
|
|
|
return ret;
|
|
}
|
|
void tegra_dsi_pending_hpd(struct tegra_dc_dsi_data *dsi);
|
|
void tegra_dsi_hpd_suspend(struct tegra_dc_dsi_data *dsi);
|
|
#endif
|