forked from rrcarlosr/Jetpack
439 lines
9.9 KiB
C
439 lines
9.9 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/debugfs.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/t194_nvg.h>
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#include <linux/tegra-mce.h>
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#include <asm/smp_plat.h>
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#include <soc/tegra/chip-id.h>
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#include "tegra19x-mce.h"
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#include "dmce_perfmon.h"
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/* Issue a NVG request with data */
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static noinline notrace void nvg_send_req_data(uint64_t req, uint64_t data)
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{
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asm volatile (
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"msr s3_0_c15_c1_2, %0 \n"
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"msr s3_0_c15_c1_3, %1 \n"
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:: "r" (req), "r" (data));
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}
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/* Issue a NVG request with no data */
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static noinline notrace void nvg_send_req(uint64_t req)
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{
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asm volatile ("msr s3_0_c15_c1_2, %0 \n" :: "r" (req));
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}
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/* Issue a NVG request to read the command response */
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static noinline notrace uint64_t nvg_get_response(void)
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{
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uint64_t ret;
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asm volatile ("mrs %0, s3_0_c15_c1_3" : "=r" (ret));
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return ret;
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}
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int tegra19x_mce_enter_cstate(u32 state, u32 wake_time)
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{
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/* use PSCI interface instead */
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return 0;
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}
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int tegra19x_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system,
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u8 force, u32 wake_mask, bool valid)
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{
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nvg_cstate_info_channel_t cstate_info = { 0 };
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/* disable preemption */
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preempt_disable();
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/* update CLUSTER_CSTATE? */
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if (cluster) {
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cstate_info.bits.cluster_state = cluster;
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cstate_info.bits.update_cluster = 1;
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}
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/* update CCPLEX_CSTATE? */
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if (ccplex) {
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cstate_info.bits.cg_cstate = ccplex;
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cstate_info.bits.update_cg = 1;
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}
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/* update SYSTEM_CSTATE? */
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if (system) {
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cstate_info.bits.system_cstate = system;
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cstate_info.bits.update_system = 1;
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}
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/* update wake mask value? */
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if (valid)
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cstate_info.bits.update_wake_mask = 1;
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/* set the wake mask */
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cstate_info.bits.wake_mask = wake_mask;
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/* set the updated cstate info */
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nvg_send_req_data(TEGRA_NVG_CHANNEL_CSTATE_INFO,
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cstate_info.flat);
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_update_crossover_time(u32 type, u32 time)
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{
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if ((type != TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND) &&
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(type != TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND) &&
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(type != TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND)) {
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pr_err("%s: unknown crossover type (%d)\n", __func__, type);
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return -EINVAL;
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}
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/* disable pre-emption*/
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preempt_disable();
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nvg_send_req_data(type, (uint64_t)time);
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/* enable pre-emption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_read_cstate_stats(u32 state, u64 *stats)
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{
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if (!stats)
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return -EINVAL;
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/* disable preemption */
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preempt_disable();
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nvg_send_req_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST,
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(uint64_t)state);
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nvg_send_req(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE);
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*stats = nvg_get_response();
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_cc3_ctrl(u32 ndiv, u32 vindex, u8 enable)
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{
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nvg_cc3_control_channel_t cc3_ctrl;
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/* disable preemption */
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preempt_disable();
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/*
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* If the enable bit is cleared, Auto-CC3 will be disabled by setting
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* the SW visible frequency request registers for all non
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* floorswept cores valid independent of StandbyWFI and disabling
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* the IDLE frequency request register. If set, Auto-CC3
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* will be enabled by setting the ARM SW visible frequency
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* request registers for all non floorswept cores to be enabled by
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* StandbyWFI or the equivalent signal, and always keeping the IDLE
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* frequency request register enabled.
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*/
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cc3_ctrl.bits.freq_req = ndiv;
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cc3_ctrl.bits.enable = !!enable;
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nvg_send_req_data(TEGRA_NVG_CHANNEL_CC3_CTRL, cc3_ctrl.flat);
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_read_versions(u32 *major, u32 *minor)
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{
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uint64_t version;
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if (!major || !minor)
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return -EINVAL;
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/* disable preemption */
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preempt_disable();
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nvg_send_req(TEGRA_NVG_CHANNEL_VERSION);
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version = nvg_get_response();
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*minor = (u32)version;
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*major = (u32)(version >> 32);
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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/* Check for valid dda channel id.*/
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static int tegra19x_check_dda_channel_id(u32 index) {
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if ((index < TEGRA_NVG_CHANNEL_DDA_SNOC_MCF) ||
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(index > TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL)) {
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pr_err("mce: invalid dda channel id: %u\n", index);
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return -EINVAL;
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}
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return 0;
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}
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int tegra19x_mce_write_dda_ctrl(u32 index, u64 value)
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{
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if (tegra19x_check_dda_channel_id(index))
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return -EINVAL;
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/* disable preemption */
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preempt_disable();
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nvg_send_req_data(index, value);
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_read_dda_ctrl(u32 index, u64* value)
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{
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if (tegra19x_check_dda_channel_id(index))
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return -EINVAL;
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if (!value)
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return -EINVAL;
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/* disable preemption */
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preempt_disable();
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nvg_send_req(index);
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*value = nvg_get_response();
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_read_l3_cache_ways(u64 *value)
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{
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/* disable preemption */
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preempt_disable();
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nvg_send_req(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL);
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*value = nvg_get_response();
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_write_l3_cache_ways(u64 data, u64 *value)
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{
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/* disable preemption */
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preempt_disable();
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nvg_send_req_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL, data);
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*value = nvg_get_response();
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_read_rt_safe_mask(u64 *rt_safe_mask)
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{
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if (!rt_safe_mask)
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return -EINVAL;
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/* disable preemption */
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preempt_disable();
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nvg_send_req(TEGRA_NVG_CHANNEL_RT_SAFE_MASK);
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*rt_safe_mask = nvg_get_response();
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_write_rt_safe_mask(u64 rt_safe_mask)
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{
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/* disable preemption */
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preempt_disable();
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nvg_send_req_data(TEGRA_NVG_CHANNEL_RT_SAFE_MASK, rt_safe_mask);
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_read_rt_window_us(u64 *rt_window_us)
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{
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if (!rt_window_us)
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return -EINVAL;
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/* disable preemption */
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preempt_disable();
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nvg_send_req(TEGRA_NVG_CHANNEL_RT_WINDOW_US);
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*rt_window_us = nvg_get_response();
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_write_rt_window_us(u64 rt_window_us)
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{
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/* disable preemption */
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preempt_disable();
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nvg_send_req_data(TEGRA_NVG_CHANNEL_RT_WINDOW_US, rt_window_us);
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_read_rt_fwd_progress_us(u64 *rt_fwd_progress_us)
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{
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if (!rt_fwd_progress_us)
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return -EINVAL;
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/* disable preemption */
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preempt_disable();
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nvg_send_req(TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US);
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*rt_fwd_progress_us = nvg_get_response();
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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int tegra19x_mce_write_rt_fwd_progress_us(u64 rt_fwd_progress_us)
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{
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/* disable preemption */
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preempt_disable();
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nvg_send_req_data(TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US,
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rt_fwd_progress_us);
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/* enable preemption */
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preempt_enable();
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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/* Dummy functions below */
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int tegra19x_mce_features_get(void *data, u64 *val) { return -ENOTSUPP; }
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int tegra19x_mce_enable_latic_set(void *data, u64 val) { return -ENOTSUPP; }
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int tegra19x_mce_coresight_cg_set(void *data, u64 val) { return -ENOTSUPP; }
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int tegra19x_mce_edbgreq_set(void *data, u64 val) { return -ENOTSUPP; }
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#define NVG_STAT_MAX_ENTRIES 10
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#define MCE_STAT_ID_SHIFT 16UL
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#define UNITGROUP_IGNORED 0
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#define UNITGROUP_CORE 1
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#define UNITGROUP_CLUSTER 2
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#define UNITGROUP_CLUSTERGROUP 3
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#define CSTAT_ENTRY(stat) NVG_STAT_QUERY_##stat
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struct cstats_info {
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char *name; /* name of the cstats */
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int id; /* NVG id */
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int units;/* No of cores; No of clusters; No of cluster groups */
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int unit_group; /* 0:Ignored; 1:core; 2:cluster; 3:cluster group */
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};
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static struct cstats_info cstats_table[] = {
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{ "SC7_ENTRIES", CSTAT_ENTRY(SC7_ENTRIES), 1, UNITGROUP_IGNORED},
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{ "SC7_RESIDENCY_SUM",
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CSTAT_ENTRY(SC7_RESIDENCY_SUM), 1, UNITGROUP_IGNORED},
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{ "CG7_ENTRIES", CSTAT_ENTRY(CG7_ENTRIES), 2, UNITGROUP_CLUSTERGROUP},
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{ "CG7_RESIDENCY_SUM",
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CSTAT_ENTRY(CG7_RESIDENCY_SUM), 2, UNITGROUP_CLUSTERGROUP},
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{ "CC6_ENTRIES", CSTAT_ENTRY(CC6_ENTRIES), 4, UNITGROUP_CLUSTER},
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{ "CC6_RESIDENCY_SUM",
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CSTAT_ENTRY(CC6_RESIDENCY_SUM), 4, UNITGROUP_CLUSTER},
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{ "C7_ENTRIES", CSTAT_ENTRY(C7_ENTRIES), 8, UNITGROUP_CORE},
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{ "C7_RESIDENCY_SUM", CSTAT_ENTRY(C7_RESIDENCY_SUM), 8, UNITGROUP_CORE},
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{ "C6_ENTRIES", CSTAT_ENTRY(C6_ENTRIES), 8, UNITGROUP_CORE},
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{ "C6_RESIDENCY_SUM", CSTAT_ENTRY(C6_RESIDENCY_SUM), 8, UNITGROUP_CORE},
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};
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int tegra19x_mce_dbg_cstats_show(struct seq_file *s, void *data)
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{
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int nr_cpus = num_present_cpus();
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int st, unit;
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u64 val;
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u32 mce_index;
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seq_printf(s, "%-25s%-15s%-10s\n", "name", "unit-id", "count/time");
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seq_puts(s, "---------------------------------------------------\n");
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for (st = 0; st < NVG_STAT_MAX_ENTRIES; st++) {
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switch (cstats_table[st].unit_group) {
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case UNITGROUP_IGNORED:
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cstats_table[st].units = 1;
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break;
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case UNITGROUP_CLUSTERGROUP:
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cstats_table[st].units = 2;
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break;
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case UNITGROUP_CLUSTER:
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/* Divide by 2 to get num of clusters
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* as t19x has 2 cores per cluster
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*/
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cstats_table[st].units = nr_cpus / 2;
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break;
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case UNITGROUP_CORE:
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cstats_table[st].units = nr_cpus;
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break;
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default:
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return -EINVAL;
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}
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for (unit = 0; unit < cstats_table[st].units; unit++) {
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mce_index = ((u32)cstats_table[st].id <<
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MCE_STAT_ID_SHIFT) + (u32)unit;
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if (tegra19x_mce_read_cstate_stats(mce_index, &val))
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pr_err("mce: failed to read cstat: %s, %x\n",
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cstats_table[st].name, mce_index);
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else
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seq_printf(s, "%-25s%-15d%-20lld\n",
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cstats_table[st].name, unit, val);
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}
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}
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return 0;
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}
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#endif /* CONFIG_DEBUG_FS */
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