forked from rrcarlosr/Jetpack
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
/*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/sched.h>
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#include <linux/version.h>
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#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 13, 0)
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#include <linux/sched/signal.h>
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#endif
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/tegra-mce.h>
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#include <linux/tegra-roc.h>
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#include <asm/cputype.h>
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#define MCE_FLUSH_CTRL 0x0
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#define MCE_FLUSH_ADDR_MATCH 0x4
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#define MCE_FLUSH_ADDR_MASK 0x8
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#define FLUSH_ADDR_MATCH_ALL (BIT(29) - 1)
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#define FLUSH_ADDR_MASK_NULL 0x0
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#define FLUSH_CTRL_CLEANINV 0x0
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#define FLUSH_CTRL_DONE_MASK BIT(3)
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#define FLUSH_CTRL_PEND_MASK BIT(2)
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#define FLUSH_CTRL_ABORT BIT(1)
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#define FLUSH_CTLR_TRIGGER BIT(0)
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#define FLUSH_POLL_DELAY 1 /* 1ms */
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static void __iomem *flush_base;
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static DEFINE_MUTEX(flush_lock);
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/**
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* Flush cache of the whole CCPLEX.
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*
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* Needed before/after large DMA transfers with non-snooping devices.
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* This function will sleep if there is outstanding flush operation.
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*
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* Returns 0 if success.
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*/
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int tegra_roc_flush_cache_all(void)
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{
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u32 ctrl;
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int ret = 0;
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if (!flush_base) {
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pr_err("tegra-roc-flush: driver is not ready yet.\n");
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return -EINVAL;
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}
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might_sleep();
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if (mutex_lock_interruptible(&flush_lock))
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return -ERESTARTSYS;
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/* Disable filtering */
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writel(FLUSH_ADDR_MATCH_ALL, flush_base + MCE_FLUSH_ADDR_MATCH);
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writel(FLUSH_ADDR_MASK_NULL, flush_base + MCE_FLUSH_ADDR_MASK);
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ctrl = readl(flush_base + MCE_FLUSH_CTRL);
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if (unlikely(ctrl & FLUSH_CTRL_PEND_MASK)) {
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pr_err("tegra-roc-flush: flush is pending.\n");
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ret = -EINVAL;
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goto unlock;
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}
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ctrl = FLUSH_CTRL_CLEANINV | FLUSH_CTLR_TRIGGER;
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writel(ctrl, flush_base + MCE_FLUSH_CTRL);
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for (;;) {
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if (signal_pending(current)) {
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ret = -ERESTARTSYS;
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goto unlock;
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}
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ctrl = readl(flush_base + MCE_FLUSH_CTRL);
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if (ctrl & FLUSH_CTRL_DONE_MASK)
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break;
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mdelay(FLUSH_POLL_DELAY);
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}
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unlock:
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mutex_unlock(&flush_lock);
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return ret;
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}
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EXPORT_SYMBOL(tegra_roc_flush_cache_all);
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static const struct of_device_id tegra_roc_flush_of_match[] = {
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{ .compatible = "nvidia,tegra186-roc-flush", },
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{},
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};
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static __init int tegra_roc_flush_init(void)
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{
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struct device_node *np;
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u32 cpuid;
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np = of_find_compatible_node(NULL, NULL,
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tegra_roc_flush_of_match[0].compatible);
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if (!np) {
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cpuid = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
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if (cpuid == MIDR_NVIDIA_DENVER)
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pr_err("tegra-roc-flush: DT required.\n");
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return -EINVAL;
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}
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flush_base = of_iomap(np, 0);
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if (!flush_base) {
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pr_err("tegra-roc-flush: failed to map device.\n");
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return -EINVAL;
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}
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of_node_put(np);
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return 0;
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}
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early_initcall(tegra_roc_flush_init);
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