forked from rrcarlosr/Jetpack
613 lines
12 KiB
C
613 lines
12 KiB
C
/*
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* drivers/misc/tegra-profiler/power_clk.c
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*
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* Copyright (c) 2013-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/cpufreq.h>
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#include <linux/clk.h>
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#include <linux/notifier.h>
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#include <linux/workqueue.h>
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#include <linux/cpu.h>
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#include <linux/timer.h>
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#include <linux/err.h>
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#include <linux/version.h>
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#include <linux/tegra_profiler.h>
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#include "power_clk.h"
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#include "quadd.h"
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#include "hrt.h"
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#include "comm.h"
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#include "debug.h"
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#define PCLK_MAX_VALUES 32
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struct power_clk_data {
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unsigned int value;
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unsigned int prev;
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};
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#define PCLK_NB_GPU 0
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#define PCLK_NB_EMC 0
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enum {
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PCLK_NB_CPU_FREQ,
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PCLK_NB_CPU_HOTPLUG,
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PCLK_NB_CPU_MAX,
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};
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#define PCLK_NB_MAX PCLK_NB_CPU_MAX
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struct power_clk_source {
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int type;
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struct clk *clkp;
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struct notifier_block nb[PCLK_NB_MAX];
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int cpu;
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int nr;
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struct power_clk_data data[PCLK_MAX_VALUES];
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atomic_t active;
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struct mutex lock;
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};
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struct power_clk_context_s {
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struct power_clk_source cpu;
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struct power_clk_source gpu;
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struct power_clk_source emc;
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struct timer_list timer;
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unsigned int period;
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unsigned int is_cpufreq : 1;
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struct quadd_ctx *quadd_ctx;
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};
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static struct power_clk_context_s power_ctx;
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static void make_sample(struct power_clk_source *s)
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{
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int i;
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u32 values[PCLK_MAX_VALUES];
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struct quadd_iovec vec;
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struct quadd_record_data record;
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struct quadd_power_rate_data *p = &record.power_rate;
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record.record_type = QUADD_RECORD_TYPE_POWER_RATE;
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p->type = (u8)s->type;
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p->time = quadd_get_time();
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p->cpu_id = (u32)s->cpu;
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p->flags = 0;
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if (s->type == QUADD_POWER_CLK_CPU) {
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p->nr_values = 1;
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values[0] = s->data[s->cpu].value;
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} else {
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p->nr_values = (u16)s->nr;
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for (i = 0; i < s->nr; i++)
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values[i] = s->data[i].value;
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}
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vec.base = values;
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vec.len = p->nr_values * sizeof(values[0]);
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quadd_put_sample(&record, &vec, 1);
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}
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static void
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make_sample_hotplug(int cpu, int is_online)
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{
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struct quadd_record_data record;
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struct quadd_hotplug_data *s = &record.hotplug;
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record.record_type = QUADD_RECORD_TYPE_HOTPLUG;
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s->cpu = cpu;
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s->is_online = is_online ? 1 : 0;
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s->time = quadd_get_time();
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s->reserved = 0;
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quadd_put_sample(&record, NULL, 0);
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}
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static inline int
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is_data_changed(struct power_clk_source *s)
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{
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int i, cpu;
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if (s->type == QUADD_POWER_CLK_CPU) {
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cpu = s->cpu;
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return (s->data[cpu].value != s->data[cpu].prev);
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}
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for (i = 0; i < s->nr; i++) {
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if (s->data[i].value != s->data[i].prev)
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return 1;
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}
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return 0;
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}
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static inline void
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update_data(struct power_clk_source *s)
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{
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int i, cpu;
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if (s->type == QUADD_POWER_CLK_CPU) {
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cpu = s->cpu;
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s->data[cpu].prev = s->data[cpu].value;
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return;
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}
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for (i = 0; i < s->nr; i++)
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s->data[i].prev = s->data[i].value;
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}
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static void check_source(struct power_clk_source *s)
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{
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if (is_data_changed(s)) {
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update_data(s);
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make_sample(s);
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}
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}
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static void
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read_source(struct power_clk_source *s, int cpu)
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{
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unsigned int value;
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switch (s->type) {
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case QUADD_POWER_CLK_CPU:
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/* update cpu frequency */
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if (cpu < 0 || cpu >= max_t(int, s->nr, nr_cpu_ids)) {
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pr_err_once("error: cpu id: %d\n", cpu);
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break;
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}
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value = cpufreq_get(cpu);
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if (!mutex_trylock(&s->lock))
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break;
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s->cpu = cpu;
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s->data[cpu].value = value;
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pr_debug("PCLK_CPU(%d), value: %u\n", cpu, s->data[cpu].value);
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check_source(s);
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mutex_unlock(&s->lock);
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break;
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case QUADD_POWER_CLK_GPU:
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/* update gpu frequency */
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if (!mutex_trylock(&s->lock))
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break;
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if (s->clkp)
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s->data[0].value =
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(unsigned int)(clk_get_rate(s->clkp) / 1000);
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pr_debug("PCLK_GPU, value: %u\n", s->data[0].value);
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s->cpu = cpu;
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check_source(s);
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mutex_unlock(&s->lock);
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break;
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case QUADD_POWER_CLK_EMC:
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/* update emc frequency */
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if (!mutex_trylock(&s->lock))
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break;
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if (s->clkp)
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s->data[0].value =
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(unsigned int)(clk_get_rate(s->clkp) / 1000);
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pr_debug("PCLK_EMC, value: %u\n", s->data[0].value);
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s->cpu = cpu;
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check_source(s);
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mutex_unlock(&s->lock);
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break;
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default:
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pr_err_once("error: invalid power_clk type\n");
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break;
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}
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}
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static int
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gpu_notifier_call(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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read_source(&power_ctx.gpu, -1);
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return NOTIFY_DONE;
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}
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static int
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emc_notifier_call(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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read_source(&power_ctx.emc, -1);
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return NOTIFY_DONE;
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}
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static void
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read_cpufreq(struct power_clk_source *s, struct cpufreq_freqs *freq)
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{
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int cpu, cpufreq;
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if (!mutex_trylock(&s->lock))
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return;
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if (!atomic_read(&s->active))
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goto out_unlock;
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cpu = freq->cpu;
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cpufreq = freq->new;
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pr_debug("cpu: %d, cpufreq: %d\n", cpu, cpufreq);
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if (cpu >= s->nr) {
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pr_err_once("error: cpu id: %d\n", cpu);
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goto out_unlock;
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}
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s->cpu = cpu;
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s->data[cpu].value = cpufreq;
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pr_debug("[%d] cpufreq: %u --> %u\n",
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cpu, freq->old, cpufreq);
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check_source(s);
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out_unlock:
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mutex_unlock(&s->lock);
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}
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static int
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cpufreq_notifier_call(struct notifier_block *nb,
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unsigned long action, void *hcpu)
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{
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struct cpufreq_freqs *freq;
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struct power_clk_source *s = &power_ctx.cpu;
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if (!atomic_read(&s->active))
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return 0;
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pr_debug("action: %lu\n", action);
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if (action == CPUFREQ_POSTCHANGE) {
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freq = hcpu;
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read_cpufreq(s, freq);
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}
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return 0;
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}
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static int
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cpu_hotplug_notifier_call(struct notifier_block *nb,
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unsigned long action, void *hcpu)
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{
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int cpu;
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struct power_clk_source *s = &power_ctx.cpu;
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if (!atomic_read(&s->active))
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return NOTIFY_DONE;
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cpu = (long)hcpu;
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pr_debug("cpu: %d, action: %lu\n", cpu, action);
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if (cpu >= s->nr) {
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pr_err_once("error: cpu id: %d\n", cpu);
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return NOTIFY_DONE;
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}
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switch (action) {
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case CPU_ONLINE:
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case CPU_ONLINE_FROZEN:
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make_sample_hotplug(cpu, 1);
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break;
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case CPU_DEAD:
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case CPU_DEAD_FROZEN:
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mutex_lock(&s->lock);
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if (atomic_read(&s->active))
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s->data[cpu].value = 0;
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mutex_unlock(&s->lock);
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make_sample_hotplug(cpu, 0);
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break;
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default:
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return NOTIFY_DONE;
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}
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return NOTIFY_OK;
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}
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static void reset_data(struct power_clk_source *s)
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{
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int i;
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for (i = 0; i < s->nr; i++) {
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s->data[i].value = 0;
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s->data[i].prev = 0;
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}
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}
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static void init_source(struct power_clk_source *s,
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int nr_values,
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unsigned int type)
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{
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s->clkp = NULL;
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s->type = type;
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s->nr = min_t(int, nr_values, PCLK_MAX_VALUES);
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atomic_set(&s->active, 0);
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mutex_init(&s->lock);
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reset_data(s);
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}
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static void
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power_clk_work_func(struct work_struct *work)
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{
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read_source(&power_ctx.gpu, -1);
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read_source(&power_ctx.emc, -1);
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}
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static DECLARE_WORK(power_clk_work, power_clk_work_func);
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static void power_clk_timer(unsigned long data)
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{
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struct timer_list *timer = &power_ctx.timer;
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schedule_work(&power_clk_work);
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timer->expires = jiffies + msecs_to_jiffies(power_ctx.period);
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add_timer(timer);
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}
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static void
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read_all_sources_work_func(struct work_struct *work)
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{
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int cpu_id;
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struct power_clk_source *s = &power_ctx.cpu;
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if (power_ctx.is_cpufreq) {
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for_each_possible_cpu(cpu_id)
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read_source(s, cpu_id);
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}
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read_source(&power_ctx.gpu, -1);
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read_source(&power_ctx.emc, -1);
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}
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static DECLARE_WORK(read_all_sources_work, read_all_sources_work_func);
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static int
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enable_clock(struct power_clk_source *s, struct notifier_block *nb,
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const char *dev_id, const char *con_id)
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{
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int ret;
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mutex_lock(&s->lock);
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s->clkp = clk_get_sys(dev_id, con_id);
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if (IS_ERR_OR_NULL(s->clkp)) {
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pr_warn("warning: could not setup clock: \"%s:%s\"\n",
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dev_id ? dev_id : "", con_id ? con_id : "");
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ret = -ENOENT;
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goto errout;
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}
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ret = clk_prepare_enable(s->clkp);
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if (ret) {
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pr_warn("warning: could not enable gpu clock\n");
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goto errout_free_clk;
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}
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#ifdef CONFIG_COMMON_CLK
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ret = clk_notifier_register(s->clkp, nb);
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if (ret) {
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pr_warn("warning: could not register clock: \"%s:%s\"\n",
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dev_id ? dev_id : "", con_id ? con_id : "");
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goto errout_disable_clk;
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}
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#endif
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reset_data(s);
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atomic_set(&s->active, 1);
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mutex_unlock(&s->lock);
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return 0;
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#ifdef CONFIG_COMMON_CLK
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errout_disable_clk:
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clk_disable_unprepare(s->clkp);
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#endif
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errout_free_clk:
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clk_put(s->clkp);
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errout:
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s->clkp = NULL;
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atomic_set(&s->active, 0);
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mutex_unlock(&s->lock);
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return ret;
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}
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static void
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disable_clock(struct power_clk_source *s, struct notifier_block *nb)
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{
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mutex_lock(&s->lock);
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if (atomic_cmpxchg(&s->active, 1, 0)) {
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if (s->clkp) {
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#ifdef CONFIG_COMMON_CLK
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clk_notifier_unregister(s->clkp, nb);
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#endif
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clk_disable_unprepare(s->clkp);
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clk_put(s->clkp);
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s->clkp = NULL;
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}
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}
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mutex_unlock(&s->lock);
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}
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int quadd_power_clk_start(void)
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{
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struct power_clk_source *s;
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struct timer_list *timer = &power_ctx.timer;
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struct quadd_parameters *param = &power_ctx.quadd_ctx->param;
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if (param->power_rate_freq == 0) {
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pr_info("power_clk is not started\n");
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return 0;
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}
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#ifdef CONFIG_COMMON_CLK
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power_ctx.period = 0;
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#else
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power_ctx.period = MSEC_PER_SEC / param->power_rate_freq;
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pr_info("pclk: use timer, freq: %u\n", param->power_rate_freq);
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#endif
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pr_info("pclk: start, cpufreq: %s\n",
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power_ctx.is_cpufreq ? "yes" : "no");
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/* setup gpu frequency */
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s = &power_ctx.gpu;
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enable_clock(s, &s->nb[PCLK_NB_GPU], "3d", NULL);
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/* setup emc frequency */
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s = &power_ctx.emc;
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enable_clock(s, &s->nb[PCLK_NB_EMC], "cpu", "emc");
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/* setup cpu frequency notifier */
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if (power_ctx.is_cpufreq) {
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s = &power_ctx.cpu;
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mutex_lock(&s->lock);
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reset_data(s);
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atomic_set(&s->active, 1);
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mutex_unlock(&s->lock);
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}
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if (power_ctx.period > 0) {
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init_timer(timer);
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timer->function = power_clk_timer;
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timer->expires = jiffies + msecs_to_jiffies(power_ctx.period);
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timer->data = 0;
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add_timer(timer);
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}
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schedule_work(&read_all_sources_work);
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return 0;
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}
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void quadd_power_clk_stop(void)
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{
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struct power_clk_source *s;
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struct quadd_parameters *param = &power_ctx.quadd_ctx->param;
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if (param->power_rate_freq == 0)
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return;
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if (power_ctx.period > 0)
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del_timer_sync(&power_ctx.timer);
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s = &power_ctx.gpu;
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disable_clock(s, &s->nb[PCLK_NB_GPU]);
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s = &power_ctx.emc;
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disable_clock(s, &s->nb[PCLK_NB_EMC]);
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if (power_ctx.is_cpufreq) {
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s = &power_ctx.cpu;
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mutex_lock(&s->lock);
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atomic_set(&s->active, 0);
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s->clkp = NULL;
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mutex_unlock(&s->lock);
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}
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pr_info("pclk: stop\n");
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}
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int quadd_power_clk_init(struct quadd_ctx *quadd_ctx)
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{
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int __maybe_unused ret;
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struct power_clk_source *s;
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s = &power_ctx.gpu;
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s->nb[PCLK_NB_GPU].notifier_call = gpu_notifier_call;
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init_source(s, 1, QUADD_POWER_CLK_GPU);
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s = &power_ctx.emc;
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s->nb[PCLK_NB_EMC].notifier_call = emc_notifier_call;
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init_source(s, 1, QUADD_POWER_CLK_EMC);
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s = &power_ctx.cpu;
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|
s->nb[PCLK_NB_CPU_FREQ].notifier_call = cpufreq_notifier_call;
|
|
s->nb[PCLK_NB_CPU_HOTPLUG].notifier_call = cpu_hotplug_notifier_call;
|
|
init_source(s, nr_cpu_ids, QUADD_POWER_CLK_CPU);
|
|
|
|
power_ctx.quadd_ctx = quadd_ctx;
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
ret = cpufreq_register_notifier(&s->nb[PCLK_NB_CPU_FREQ],
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
if (ret < 0) {
|
|
pr_warn("CPU freq registration failed: %d\n", ret);
|
|
power_ctx.is_cpufreq = 0;
|
|
} else {
|
|
power_ctx.is_cpufreq = 1;
|
|
}
|
|
#else
|
|
power_ctx.is_cpufreq = 0;
|
|
#endif
|
|
quadd_ctx->pclk_cpufreq = power_ctx.is_cpufreq;
|
|
|
|
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)
|
|
register_cpu_notifier(&s->nb[PCLK_NB_CPU_HOTPLUG]);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
void quadd_power_clk_deinit(void)
|
|
{
|
|
struct power_clk_source *s = &power_ctx.cpu;
|
|
|
|
quadd_power_clk_stop();
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
if (power_ctx.is_cpufreq)
|
|
cpufreq_unregister_notifier(&s->nb[PCLK_NB_CPU_FREQ],
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
#endif
|
|
|
|
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)
|
|
unregister_cpu_notifier(&s->nb[PCLK_NB_CPU_HOTPLUG]);
|
|
#endif
|
|
}
|