forked from rrcarlosr/Jetpack
241 lines
7.1 KiB
C
241 lines
7.1 KiB
C
/*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2 of the license, or
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* (at your option) any later version.
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*
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* this program is distributed in the hope that it will be useful, but without
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* any warranty; without even the implied warranty of merchantability or
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* fitness for a particular purpose. see the gnu general public license for
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* more details.
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*
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* you should have received a copy of the gnu general public license along
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* with this program; if not, write to the free software foundation, inc.,
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* 51 franklin street, fifth floor, boston, ma 02110-1301, usa.
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*/
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#ifndef __TEGRA18x_FUSE_OFFSETS_H
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#define __TEGRA18x_FUSE_OFFSETS_H
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#include <soc/tegra/chip-id.h>
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#include <soc/tegra/pmc.h>
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/* private_key4 */
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#define DEVKEY_START_OFFSET 0x2A
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#define DEVKEY_START_BIT 12
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/* arm_debug_dis */
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#define JTAG_START_OFFSET 0x0
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#define JTAG_START_BIT 3
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/* security_mode */
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#define ODM_PROD_START_OFFSET 0x0
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#define ODM_PROD_START_BIT 11
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/* boot_device_info */
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#define SB_DEVCFG_START_OFFSET 0x4f
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#define SB_DEVCFG_START_BIT 23
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#define SB_BOOT_DEV_CFG_SIZE_BITS 24
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/* reserved_sw[2:0] */
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#define SB_DEVSEL_START_OFFSET 0x2C
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#define SB_DEVSEL_START_BIT 28
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/* private_key0 -> private_key3 (SBK) */
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#define SBK_START_OFFSET 0x4b
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#define SBK_START_BIT 23
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/* reserved_sw[7:4] */
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#define SW_RESERVED_START_OFFSET 0x50
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#define SW_RESERVED_START_BIT 15
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#define SW_RESERVED_SIZE_BITS 12
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/* reserved_sw[3] */
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#define IGNORE_DEVSEL_START_OFFSET 0x2E
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#define IGNORE_DEVSEL_START_BIT 7
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/* public key */
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#define PUBLIC_KEY_START_OFFSET 0x43
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#define PUBLIC_KEY_START_BIT 23
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/* pkc_disable */
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#define PKC_DISABLE_START_OFFSET 0x52
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#define PKC_DISABLE_START_BIT 7
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/* video vp8 enable */
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#define VP8_ENABLE_START_OFFSET 0x2E
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#define VP8_ENABLE_START_BIT 4
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/* odm lock */
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#define ODM_LOCK_START_OFFSET 0x0
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#define ODM_LOCK_START_BIT 6
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/* reserved_odm0 -> reserved_odm7 */
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#define ODM_RESERVED_DEVSEL_START_OFFSET 0x2
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#define ODM_RESERVED_START_BIT 2
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#define BOOT_SECURITY_INFO_START_OFFSET 0x0
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#define BOOT_SECURITY_INFO_START_BIT 16
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#define FUSE_VENDOR_CODE 0x200
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#define FUSE_VENDOR_CODE_MASK 0xf
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#define FUSE_FAB_CODE 0x204
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#define FUSE_FAB_CODE_MASK 0x3f
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#define FUSE_LOT_CODE_0 0x208
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#define FUSE_LOT_CODE_1 0x20c
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#define FUSE_WAFER_ID 0x210
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#define FUSE_WAFER_ID_MASK 0x3f
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#define FUSE_X_COORDINATE 0x214
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#define FUSE_X_COORDINATE_MASK 0x1ff
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#define FUSE_Y_COORDINATE 0x218
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#define FUSE_Y_COORDINATE_MASK 0x1ff
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#define FUSE_GPU_INFO 0x390
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#define FUSE_GPU_INFO_MASK (1<<2)
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#define FUSE_SPARE_BIT 0x380
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/* fuse registers used in public fuse data read API */
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#define FUSE_FT_REV 0x128
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#define FUSE_CP_REV 0x190
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/* fuse spare bits are used to get Tj-ADT values */
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#define NUM_TSENSOR_SPARE_BITS 28
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/* tsensor calibration register */
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#define FUSE_TSENSOR_CALIB_0 0x198
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/* sparse realignment register */
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#define FUSE_SPARE_REALIGNMENT_REG_0 0x37c
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/* tsensor8_calib */
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#define FUSE_TSENSOR_CALIB_8 0x280
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#define FUSE_BASE_CP_SHIFT 0
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#define FUSE_BASE_CP_MASK 0x3ff
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#define FUSE_BASE_FT_SHIFT 10
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#define FUSE_BASE_FT_MASK 0x7ff
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#define FUSE_SHIFT_CP_SHIFT 0
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#define FUSE_SHIFT_CP_MASK 0x3f
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#define FUSE_SHIFT_CP_BITS 6
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#define FUSE_SHIFT_FT_SHIFT 21
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#define FUSE_SHIFT_FT_MASK 0x1f
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#define FUSE_SHIFT_FT_BITS 5
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#define TEGRA_FUSE_SUPPLY "dummy"
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#define PGM_TIME_US 12
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#define FUSE_SIZE_IN_BITS (6 * 1024)
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#define FUSE_PATCH_START_ADDRESS ((FUSE_SIZE_IN_BITS - 32)/32)
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#define FUSE_MAX_PATCH_PAYLOAD (2560 >> 5)
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#define FUSE_FIRST_BOOTROM_PATCH_SIZE_REG 0x19c
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#define FUSE_PATCH_C_MASK 0x000F0000
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#define FUSE_PATCH_C_SHIFT 16
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#define FUSE_NEXT_PATCH_SHIFT 25
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#define FUSE_CAM_ADDR_MASK 0xFFFF0000
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#define FUSE_CAM_ADDR_SHIFT 16
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#define FUSE_CAM_DATA_MASK 0x0000FFFF
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#define FUSE_CHIP_REG_START_OFFSET 0x100
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#define FUSE_CHIP_REG_END_OFFSET 0x3FC
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#define FUSE_OVERRIDE_REG_START_ADDR 0xFFFF
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#define FUSE_OVERRIDE_REG_END_ADDR 0xFE80
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#define FUSE_OVERRIDE_MSB16_MASK 0xFFFF0000
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#define FUSE_OVERRIDE_LSB16_MASK 0x0000FFFF
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#define FUSE_OVERRIDE_MSB16_SHIFT 16
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#define FUSE_TOT_WORDS 192
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#define FUSE_OPT_SUBREVISION 0x248
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#define FUSE_OPT_SUBREVISION_MASK 0xF
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extern void tegra_pmc_fuse_disable_mirroring(void);
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extern void tegra_pmc_fuse_enable_mirroring(void);
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static const u32 UINT_BITS = 32;
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static const u32 LOG2_UINT_BITS = 5;
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static const u32 INSIDE_UINT_OFFSET_MASK = 0x1F;
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static const u32 H16_BITS = 16;
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static const u32 H16_START_OFFSET = 1 << (16 - 2);
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static const u32 H16_ECC_MASK = 0xFFF0FFFFU;
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static const u32 H16_PARITY_MASK = 0x00008000U;
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static const u32 H16_H_MASK = 0x00007FFFU;
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static const u32 H5_CODEWORD_SIZE = 12;
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static const u32 H5_BIT_OFFSET = 20;
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/* the H5 code word is mapped on MSB of a word */
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static const u32 H5_CODEWORD_MASK = 0xFFF00000U;
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static const u32 H5_PARITY_MASK = 0x01000000U;
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static const u32 H_NO_ERROR;
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static const u32 H_CORRECTED_ERROR = 1;
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static const u32 H_UNCORRECTED_ERROR_ODD = 2;
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static const u32 H_UNCORRECTED_ERROR_EVEN = 3;
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enum override_indicator {
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FUSE_OVERRIDE_NONE = 0,
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FUSE_OVERRIDE_LSB16,
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FUSE_OVERRIDE_MSB16,
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FUSE_OVERRIDE_WORD,
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};
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struct fuse_chip_option_override_regs {
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enum override_indicator override_flag;
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u32 override_data;
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};
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static const u32 h5syndrome_table[] = {
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0x1, 0x2, 0x4, 0x8,
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0x0, 0x3, 0x5, 0x6,
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0x7, 0x9, 0xA, 0xB };
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static DEVICE_ATTR(public_key, 0440, tegra_fuse_show, tegra_fuse_store);
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static DEVICE_ATTR(pkc_disable, 0440, tegra_fuse_show, tegra_fuse_store);
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static DEVICE_ATTR(odm_lock, 0440, tegra_fuse_show, tegra_fuse_store);
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static DEVICE_ATTR(boot_sec_info, 0440, tegra_fuse_show, tegra_fuse_store);
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static int tegra_fuse_add_sysfs_variables(struct platform_device *pdev,
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bool odm_security_mode)
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{
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dev_attr_odm_lock.attr.mode = 0640;
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if (odm_security_mode) {
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dev_attr_public_key.attr.mode = 0440;
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dev_attr_pkc_disable.attr.mode = 0440;
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dev_attr_boot_sec_info.attr.mode = 0440;
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} else {
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dev_attr_public_key.attr.mode = 0640;
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dev_attr_pkc_disable.attr.mode = 0640;
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dev_attr_boot_sec_info.attr.mode = 0640;
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}
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CHK_ERR(&pdev->dev, sysfs_create_file(&pdev->dev.kobj,
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&dev_attr_public_key.attr));
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CHK_ERR(&pdev->dev, sysfs_create_file(&pdev->dev.kobj,
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&dev_attr_pkc_disable.attr));
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CHK_ERR(&pdev->dev, sysfs_create_file(&pdev->dev.kobj,
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&dev_attr_odm_lock.attr));
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CHK_ERR(&pdev->dev, sysfs_create_file(&pdev->dev.kobj,
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&dev_attr_boot_sec_info.attr));
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return 0;
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}
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static int tegra_fuse_rm_sysfs_variables(struct platform_device *pdev)
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{
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sysfs_remove_file(&pdev->dev.kobj, &dev_attr_public_key.attr);
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sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pkc_disable.attr);
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sysfs_remove_file(&pdev->dev.kobj, &dev_attr_odm_lock.attr);
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sysfs_remove_file(&pdev->dev.kobj, &dev_attr_boot_sec_info.attr);
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return 0;
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}
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static int tegra_fuse_ch_sysfs_perm(struct device *dev, struct kobject *kobj)
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{
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CHK_ERR(dev, sysfs_chmod_file(kobj,
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&dev_attr_public_key.attr, 0440));
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CHK_ERR(dev, sysfs_chmod_file(kobj,
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&dev_attr_pkc_disable.attr, 0440));
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return 0;
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}
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#endif /* __TEGRA18x_FUSE_OFFSETS_H */
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