forked from rrcarlosr/Jetpack
123 lines
3.2 KiB
C
123 lines
3.2 KiB
C
/*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk/tegra.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <soc/tegra/chip-id.h>
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#include <linux/tegra-aon-clk.h>
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#include "clk.h"
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#include "clk-tegra-bpmp.h"
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/* Needed for a nvdisp linsim clock hack */
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#define CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0 0x800008
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0 0x801004
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static void __init tegra_bpmp_staged_clock_init(struct device_node *np)
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{
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tegra_bpmp_clk_init(np, 1);
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}
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static void __init tegra_bpmp_clock_init(struct device_node *np)
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{
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tegra_bpmp_clk_init(np, 0);
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}
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static void __init tegra186_clock_init(struct device_node *np)
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{
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tegra_bpmp_clk_init(np, 0);
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/* Nvdisp sim clock hack */
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if (tegra_platform_is_fpga()) {
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void __iomem *base;
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("ioremap Tegra186 CAR failed\n");
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return;
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}
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writel(0x3ff, base + CLK_RST_CONTROLLER_RST_DEV_NVDISPLAY0_CLR_0);
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writel(0xf, base + CLK_RST_CONTROLLER_CLK_OUT_ENB_NVDISPLAY0_SET_0);
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}
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}
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static void __init tegra_of_fake_clks_init(struct device_node *np)
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{
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int r;
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r = tegra_fake_clks_init(np);
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pr_info("tegra_fake_clks init %s\n", r ? "failed" : "ok");
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}
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static const struct of_device_id tegra_clock_ids[] __initconst = {
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{ .compatible = "nvidia,tegra-fake-clks",
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.data = tegra_of_fake_clks_init },
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{ .compatible = "nvidia,tegra18x-car",
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.data = tegra186_clock_init },
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{ .compatible = "nvidia,tegra-bpmp-clks",
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.data = tegra_bpmp_clock_init },
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{ .compatible = "nvidia,tegra-bpmp-staged-clks",
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.data = tegra_bpmp_staged_clock_init },
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#ifdef CONFIG_TEGRA_AON
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{ .compatible = "nvidia,tegra-aon-clks",
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.data = tegra_aon_clk_init
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},
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#endif
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{}
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};
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#ifdef CONFIG_TEGRA_CLK_DEBUG
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static struct tegra_pto_table emc_pto = {
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.clk_id = 0, .divider = 1, .pto_id = 36,
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};
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#endif
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int __init tegra_bpmp_of_clk_init(void)
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{
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struct device_node *dn;
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struct clk *emc_clk;
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of_clk_init(tegra_clock_ids);
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/* see if we have EMC proxy in DT */
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dn = of_find_compatible_node(NULL, NULL, "nvidia,tegra-bpmp-emc-clk");
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if (dn == NULL) {
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goto out;
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}
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emc_clk = of_clk_get(dn, 0);
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if (IS_ERR_OR_NULL(emc_clk)) {
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pr_err("%s: no bpmp emc clock.\n", __func__);
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return -ENODEV;
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}
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clk_register_clkdev(emc_clk, "emc", 0);
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#ifdef CONFIG_TEGRA_CLK_DEBUG
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tegra_clk_debugfs_add(emc_clk);
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tegra_register_pto(emc_clk, &emc_pto);
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#endif
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out:
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return 0;
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}
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arch_initcall(tegra_bpmp_of_clk_init);
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