forked from rrcarlosr/Jetpack
166 lines
5.3 KiB
Plaintext
166 lines
5.3 KiB
Plaintext
/*
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* tegra186-soc-uart.dtsi: Tegra186 soc dtsi file for UART instances
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*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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/ {
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uarta: serial@3100000 {
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compatible = "nvidia,tegra186-hsuart";
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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reg = <0x0 0x03100000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <0 TEGRA186_IRQ_UARTA 0x04>;
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nvidia,memory-clients = <14>;
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dmas = <&gpcdma 8>, <&gpcdma 8>;
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dma-names = "rx", "tx";
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clocks = <&tegra_car TEGRA186_CLK_UARTA>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
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clock-names = "serial", "parent";
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resets = <&tegra_car TEGRA186_RESET_UARTA>;
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reset-names = "serial";
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status = "disabled";
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nvidia,tolerance-low-range = <0>;
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nvidia,tolerance-high-range = <4>;
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nvidia,adjust-baud-rates = <115200 115200 100>;
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};
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uartb: serial@3110000 {
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compatible = "nvidia,tegra186-hsuart";
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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reg = <0x0 0x03110000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <0 TEGRA186_IRQ_UARTB 0x04>;
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nvidia,memory-clients = <14>;
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dmas = <&gpcdma 9>, <&gpcdma 9>;
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dma-names = "rx", "tx";
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clocks = <&tegra_car TEGRA186_CLK_UARTB>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
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clock-names = "serial", "parent";
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resets = <&tegra_car TEGRA186_RESET_UARTB>;
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reset-names = "serial";
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status = "disabled";
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nvidia,tolerance-low-range = <0>;
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nvidia,tolerance-high-range = <4>;
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nvidia,adjust-baud-rates = <115200 115200 100>;
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};
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uartc: serial@c280000 {
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compatible = "nvidia,tegra186-hsuart";
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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reg = <0x0 0xc280000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <0 TEGRA186_IRQ_UARTC 0x04>;
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nvidia,memory-clients = <14>;
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dmas = <&gpcdma 3>, <&gpcdma 3>;
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dma-names = "rx", "tx";
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clocks = <&tegra_car TEGRA186_CLK_UARTC>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
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clock-names = "serial", "parent";
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resets = <&tegra_car TEGRA186_RESET_UARTC>;
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reset-names = "serial";
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status = "disabled";
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nvidia,tolerance-low-range = <0>;
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nvidia,tolerance-high-range = <4>;
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nvidia,adjust-baud-rates = <115200 115200 100>;
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};
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uartd: serial@3130000 {
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compatible = "nvidia,tegra186-hsuart";
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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reg = <0x0 0x03130000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <0 TEGRA186_IRQ_UARTD 0x04>;
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nvidia,memory-clients = <14>;
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dmas = <&gpcdma 19>, <&gpcdma 19>;
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dma-names = "rx", "tx";
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clocks = <&tegra_car TEGRA186_CLK_UARTD>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
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clock-names = "serial", "parent";
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resets = <&tegra_car TEGRA186_RESET_UARTD>;
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reset-names = "serial";
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status = "disabled";
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nvidia,tolerance-low-range = <0>;
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nvidia,tolerance-high-range = <4>;
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nvidia,adjust-baud-rates = <115200 115200 100>;
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};
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uarte: serial@3140000 {
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compatible = "nvidia,tegra186-hsuart";
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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reg = <0x0 0x03140000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <0 TEGRA186_IRQ_UARTE 0x04>;
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nvidia,memory-clients = <14>;
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dmas = <&gpcdma 20>, <&gpcdma 20>;
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dma-names = "rx", "tx";
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clocks = <&tegra_car TEGRA186_CLK_UARTE>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
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clock-names = "serial", "parent";
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resets = <&tegra_car TEGRA186_RESET_UARTE>;
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reset-names = "serial";
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status = "disabled";
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nvidia,tolerance-low-range = <0>;
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nvidia,tolerance-high-range = <4>;
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nvidia,adjust-baud-rates = <115200 115200 100>;
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};
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uartf: serial@3150000 {
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compatible = "nvidia,tegra186-hsuart";
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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reg = <0x0 0x03150000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <0 TEGRA186_IRQ_UARTF 0x04>;
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nvidia,memory-clients = <14>;
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dmas = <&gpcdma 12>, <&gpcdma 12>;
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dma-names = "rx", "tx";
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clocks = <&tegra_car TEGRA186_CLK_UARTF>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
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clock-names = "serial", "parent";
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resets = <&tegra_car TEGRA186_RESET_UARTF>;
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reset-names = "serial";
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status = "disabled";
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nvidia,tolerance-low-range = <0>;
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nvidia,tolerance-high-range = <4>;
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nvidia,adjust-baud-rates = <115200 115200 100>;
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};
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uartg: serial@c290000 {
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compatible = "nvidia,tegra186-hsuart";
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iommus = <&smmu TEGRA_SID_GPCDMA_0>;
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reg = <0x0 0xc290000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <0 TEGRA186_IRQ_UARTG 0x04>;
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nvidia,memory-clients = <14>;
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dmas = <&gpcdma 2>, <&gpcdma 2>;
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dma-names = "rx", "tx";
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clocks = <&tegra_car TEGRA186_CLK_UARTG>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>;
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clock-names = "serial", "parent";
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resets = <&tegra_car TEGRA186_RESET_UARTG>;
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reset-names = "serial";
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status = "disabled";
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nvidia,tolerance-low-range = <0>;
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nvidia,tolerance-high-range = <4>;
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nvidia,adjust-baud-rates = <115200 115200 100>;
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};
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combined-uart {
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compatible = "nvidia,tegra186-combined-uart";
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reg = <0x0 0x3c10000 0x0 0x4 /* TOP0_HSP_SM_0_1_BASE */
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0x0 0xc168000 0x0 0x4 /* AON_HSP_SM_1_BASE */
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0x0 0x3c00000 0x0 0x1000>; /* TOP0_HSP_COMMON_BASE */
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interrupts = <0 120 0x04>;
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status = "okay";
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};
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};
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