forked from rrcarlosr/Jetpack
161 lines
3.8 KiB
Plaintext
161 lines
3.8 KiB
Plaintext
/*
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* arch/arm64/boot/dts/tegra186-cpus-2D4A.dtsi
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*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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*/
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#include "tegra186-a57-cpuidle.dtsi"
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#include "tegra186-denver-cpuidle.dtsi"
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&denver_0>;
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};
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core1 {
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cpu = <&denver_1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_a57_0>;
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};
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core1 {
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cpu = <&cpu_a57_1>;
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};
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core2 {
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cpu = <&cpu_a57_2>;
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};
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core3 {
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cpu = <&cpu_a57_3>;
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};
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};
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};
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denver_0: cpu@0 {
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device_type = "cpu";
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compatible = "nvidia,denver", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&DENVER_C6 &DENVER_C7>;
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cpu-ipc = <1024>;
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next-level-cache = <&L2_DENVER>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_DENVER &CPU_COST_DENVER>;
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};
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denver_1: cpu@1 {
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device_type = "cpu";
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compatible = "nvidia,denver", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&DENVER_C6 &DENVER_C7>;
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cpu-ipc = <1024>;
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next-level-cache = <&L2_DENVER>;
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capacity-dmips-mhz = <1024>;
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sched-energy-costs = <&CPU_COST_DENVER &CPU_COST_DENVER>;
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};
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cpu_a57_0: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a57-64bit", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&A57_C7>;
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cpu-ipc = <752>;
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next-level-cache = <&L2_A57>;
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capacity-dmips-mhz = <752>;
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sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
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};
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cpu_a57_1: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a57-64bit", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&A57_C7>;
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cpu-ipc = <752>;
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next-level-cache = <&L2_A57>;
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capacity-dmips-mhz = <752>;
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sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
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};
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cpu_a57_2: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a57-64bit", "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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cpu-idle-states = <&A57_C7>;
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cpu-ipc = <752>;
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next-level-cache = <&L2_A57>;
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capacity-dmips-mhz = <752>;
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sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
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};
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cpu_a57_3: cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a57-64bit", "arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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cpu-idle-states = <&A57_C7>;
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cpu-ipc = <752>;
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next-level-cache = <&L2_A57>;
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capacity-dmips-mhz = <752>;
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sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
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};
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L2_A57: l2-cache0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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};
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L2_DENVER: l2-cache1 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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};
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};
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arm-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 320 0x4>,
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<0 321 0x4>,
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<0 296 0x4>,
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<0 297 0x4>,
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<0 298 0x4>,
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<0 299 0x4>;
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interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
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&{/cpus/cpu@2} &{/cpus/cpu@3}
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&{/cpus/cpu@4} &{/cpus/cpu@5}>;
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};
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denver-pmu {
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compatible = "nvidia,denver15-pmu";
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interrupts = <0 290 0x4>;
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interrupt-affinity = <&{/cpus/cpu@0}>;
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};
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#include "tegra186-cpus-energy-2D4A.dtsi"
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};
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