forked from rrcarlosr/Jetpack
84 lines
2.1 KiB
Plaintext
84 lines
2.1 KiB
Plaintext
/*
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* arch/arm64/boot/dts/tegra186-soc/tegra186-a57-cpuidle.dtsi
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*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/ {
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cpus {
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A57_CORE_POWER_STATES: a57_core_power_states {
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compatible = "nvidia,tegra186-cpuidle-a57";
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A57_C1: c1 {
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compatible = "nvidia,tegra186-cpuidle-a57";
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state-name = "Clock gated";
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wakeup-latency-us = <1>;
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min-residency-us = <1>;
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power = <70>;
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pmstate = <0x1>;
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status = "okay";
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};
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A57_C7: c7 {
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compatible = "nvidia,tegra186-cpuidle-a57";
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state-name = "Core powergate";
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wakeup-latency-us = <130>;
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min-residency-us = <0xffffffff>;
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power = <60>;
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pmstate = <0x7>;
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arm,psci-suspend-param= <0x40000007>;
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status = "okay";
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};
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};
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a57_cluster_power_states {
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compatible = "nvidia,tegra186-cpuidle-a57-cluster";
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cc1 {
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state-name = "Cluster clock gated";
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wakeup-latency-us = <1>;
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min-residency-us = <1>;
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power = <65>;
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pmstate = <0x1>;
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status = "okay";
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};
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cc6 {
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state-name = "Cluster powergate";
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wakeup-latency-us = <350>;
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min-residency-us = <5000>;
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power = <19>;
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pmstate = <0x6>;
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status = "okay";
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};
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cc7 {
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state-name = "Cluster railgate";
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wakeup-latency-us = <80>;
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min-residency-us = <800>;
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power = <5>;
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pmstate = <0x7>;
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status = "disabled";
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};
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};
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a57_crossover_thresholds {
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compatible = "nvidia,tegra186-cpuidle-a57-thresholds";
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thresholds {
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crossover_cc1_cc6 = <5000>;
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crossover_cc1_cc7 = <700>;
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};
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};
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};
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};
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