forked from rrcarlosr/Jetpack
102 lines
3.0 KiB
Plaintext
102 lines
3.0 KiB
Plaintext
/*
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* Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <t19x-common-modules/tegra194-camera-imx274-hdmi.dtsi>
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#include "dt-bindings/clock/tegra194-clock.h"
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#define CAM0_RST_HDMI TEGRA194_MAIN_GPIO(H, 4)
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#define CAM1_RST_HDMI TEGRA194_MAIN_GPIO(T, 6)
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#define CAM2_RST_HDMI TEGRA194_MAIN_GPIO(Q, 6) /* 40-pin conn., pin 22 */
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#define TC358840_INT TEGRA194_MAIN_GPIO(Q, 1) /* 40-pin conn., pin 7 */
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/* camera control gpio definitions */
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/ {
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i2c@3180000 {
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imx274_a@1a {
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp_clks TEGRA194_CLK_EXTPERIPH2>,
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<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
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clock-names = "extperiph2", "pllp_grtba";
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mclk = "extperiph2";
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status = "okay";
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reset-gpios = <&tegra_main_gpio CAM1_RST_HDMI GPIO_ACTIVE_HIGH>;
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vana-supply = <&p2822_avdd_cam_2v8>;
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vif-supply = <&p2822_vdd_1v8_cvb>;
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/* rework: also enables VDD_1V_SATA_PHY (1.18 V) */
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vdig-supply = <&p2822_vdd_1v8_cvb>;
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};
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tc358840@1f {
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single-source-max-width = "1920";
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mclk = "extperiph2";
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cam2_rst = <&tegra_main_gpio CAM2_RST_HDMI GPIO_ACTIVE_LOW>;
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vif-supply = <&p2822_vdd_1v8_cvb>;
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/* rework: also enables VDD_1V_SATA_PHY (1.18 V) */
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vdig-supply = <&p2822_vdd_1v8_cvb>;
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reset-gpios = <&tegra_main_gpio CAM0_RST_HDMI GPIO_ACTIVE_HIGH>;
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interrupt-parent = <&tegra_main_gpio>;
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interrupts = <TC358840_INT GPIO_ACTIVE_HIGH>;
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refclk_hz = <40000000>; /* 40 - 50 MHz */
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ddc5v_delay = <1>; /* 50 ms */
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/* HDCP */
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/* TODO: Not yet implemented */
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enable_hdcp = <0>;
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/* CSI Output */
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csi_port = <1>; /* Enable TX0 only */
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lineinitcnt = <0x00000FA0>;
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lptxtimecnt = <0x00000004>;
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tclk_headercnt = <0x00180203>;
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tclk_trailcnt = <0x00040005>;
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ths_headercnt = <0x000D0004>;
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twakeup = <0x00003E80>;
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tclk_postcnt = <0x0000000A>;
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ths_trailcnt = <0x00080006>;
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hstxvregcnt = <0x00000020>;
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btacnt = <0>;
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/* PLL */
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/* Bps per lane is (refclk_hz / pll_prd) * pll_fbd */
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pll_prd = <10>;
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pll_fbd = <230>;
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pll_frs = <0>;
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};
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};
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gpio@2200000 {
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camera-control-output-high {
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status = "okay";
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gpio-hog;
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gpios = <CAM1_RST_HDMI 0>;
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output-high;
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label = "cam1-rst";
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};
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camera-control-input {
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status = "okay";
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gpio-hog;
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gpios = <TC358840_INT 0>;
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input;
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label = "cam-input-p2";
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};
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};
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};
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