forked from rrcarlosr/Jetpack
31 lines
666 B
C
31 lines
666 B
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* P3041 DS board configuration file
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*
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*/
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#define CONFIG_P3041DS
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#define CONFIG_PHYS_64BIT
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#define CONFIG_PPC_P3041
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#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
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#define CONFIG_MMC
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_FSL_SATA_V2
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#define CONFIG_PCIE3
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#define CONFIG_PCIE4
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#define CONFIG_SYS_DPAA_RMAN
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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#include "corenet_ds.h"
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