forked from rrcarlosr/Jetpack
70 lines
2.6 KiB
Plaintext
70 lines
2.6 KiB
Plaintext
Tegra AGIC Interrupt Controller Bindings
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----------------------------------------
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AGIC is based on generic interrupt controller ARM IP GIC400. The
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GIC-400 complies to AMBA AXI4 protocol and Version 2 of the ARM
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GIC Architecture Specification. The GIC-400 implements the GICv2
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Security Extension.
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Required properties:
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- compatible: should be set to "nvidia,tegra18x-agic"
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- reg: should contain AGIC distributor and cpu interface base
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address
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- interrupt-controller: detect this node as an interrupt-controller
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- no-gic-extension: This gic is standalone int controller and does
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not have external interrupt controller to support.
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- not-per-cpu: This gic is shared between the CPU's and the adsp and
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does not provide per-cpu interface.
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- interrupts: The Agic is a secondary GIC, hence requires the
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interrupt number which is wired to the primary GIC.
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Example:
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tegra_agic: agic-controller@2a41000 {
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compatible = "nvidia,tegra18x-agic";
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interrupt-controller;
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#interrupt-cells = <4>;
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no-gic-extension;
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not-per-cpu;
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reg = <0x0 0x02a41000 0x0 0x1000>,
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<0x0 0x02a42000 0x0 0x2000>;
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interrupts = <0 145 0xf04>;
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status = "disabled";
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};
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The devices using AGIC as interrupt-parent need to add a 4 cell property
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for an interrupt to be used. The first 3 cell properties are same as that
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for a GIC interrupt. The last cell represents the default routing of the
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interrupt.
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Example:
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adsp@2993000 {
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compatible = "nvidia,tegra18x-adsp";
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interrupt-parent = <&tegra_agic>;
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interrupts = <GIC_SPI INT_AMISC_MBOX_EMPTY1 IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_HOST_INTF0>, /* MBOX SEND */
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<GIC_SPI INT_AMISC_MBOX_FULL0 IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_HOST_INTF0>, /* MBOX RECV */
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<GIC_SPI INT_ATKE_WDT_IRQ IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_HOST_INTF0>, /* ATKE Watchdog */
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<GIC_SPI INT_WFI IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_HOST_INTF0>, /* WFI */
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<GIC_SPI INT_AMC_ERR IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_HOST_INTF0>, /* AMC ERR IRQ */
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<GIC_SPI INT_ADSP_ACTMON IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_HOST_INTF0>, /* ADSP ACTMON IRQ */
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<GIC_SPI INT_AMISC_MBOX_EMPTY0 IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_ADSP>, /* ADSP MBOX SEND */
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<GIC_SPI INT_AMISC_MBOX_FULL1 IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_ADSP>, /* ADSP MBOX RECV */
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<GIC_SPI INT_AMISC_MBOX_FULL2 IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_ADSP>, /* ADSP FIQ HANDLER */
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<GIC_SPI INT_ATKE_TMR0 IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_ADSP>, /* ATKE TIMER 0 */
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<GIC_SPI INT_ATKE_TMR1 IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_ADSP>, /* ATKE TIMER 1 */
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<GIC_SPI INT_SHSP2APE_DB IRQ_TYPE_LEVEL_HIGH
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ROUTE_TO_ADSP>; /* SHSP2APE */
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};
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