/*
 * tegra194-soc-sim.dtsi: Simulation and Emulation SOC base
 *			  DTSI file used for all sim DTSI.
 *
 * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#include <tegra194-soc/tegra194-soc-base.dtsi>

/ {
	reserved-memory {
		grid-of-semaphores {
			status = "okay";
		};
	};

	tegra-carveouts {
		status = "okay";
	};

	tegra-cvnas {
		status = "okay";
	};

	power-domain {
		status = "okay";
	};

	interrupt-controller {
		status = "okay";
	};

	mc {
		status = "okay";
	};

	mc_sid@2c00000 {
		status = "okay";
	};

	iommu@12000000 {
		status = "okay";
	};

	tegra-hsp@c150000 {
		status = "okay";
	};

	tegra-hsp@3c00000 {
		status = "okay";
	};

	host1x {
		ctx0 {
			status = "okay";
		};

		ctx1 {
			status = "okay";
		};

		ctx2 {
			status = "okay";
		};

		ctx3 {
			status = "okay";
		};

		ctx4 {
			status = "okay";
		};

		ctx5 {
			status = "okay";
		};

		ctx6 {
			status = "okay";
		};

		ctx7 {
			status = "okay";
		};
	};

	psci {
		status = "okay";
	};

	cpus {
		/*
		 * Override the MPIDR value for simulator because MPIDR
		 * value returned by the CPU on simulator is different
		 * from the one in soc-base dtsi.
		 */
		cpu@0 {
			reg = <0x0 0x0>;
		};
	};

	gv11b {
		status = "okay";
	};

	mc {
		/delete-property/ ranges;
		/delete-node/ mssnvlink@1f20000;
	};
};