/* * tegra186-soc-actmon.dtsi: Tegra186 soc dtsi file for central actmon instances * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ / { actmon@d230000 { status = "disabled"; #address-cells = <2>; #size-cells = <2>; /* tegra186 central actmon */ compatible = "nvidia,tegra186-cactmon"; reg = <0x0 0x0d230000 0x0 0x1000>; /* ACTMON_BASE */ interrupts = <0 TEGRA186_IRQ_ACTMON IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA186_CLK_ACTMON>; clock-names = "actmon"; resets = <&tegra_car TEGRA186_RESET_ACTMON>; reset-names = "actmon_rst"; nvidia,sample_period = /bits/ 8 <20>; mc_all { /* MC_ALL actmon device */ #address-cells = <1>; #size-cells = <0>; nvidia,reg_offs = <0x100>; nvidia,irq_mask = <0x2>; /* EMC_PLLP_FREQ + 2000 */ nvidia,suspend_freq = <204000>; nvidia,boost_freq_step = <204000>; nvidia,boost_up_coef = <200>; nvidia,boost_down_coef = <50>; nvidia,boost_up_threshold = <30>; nvidia,boost_down_threshold = <20>; nvidia,up_wmark_window = /bits/ 8 <3>; nvidia,down_wmark_window = /bits/ 8 <2>; nvidia,avg_window_log2 = /bits/ 8 <6>; /* * count_weight(W) = no of dram clks needed to access N atoms * N = atoms per dvfs pulse = (2^7+1) = 256 atoms * 1 atom = 64 bytes * t186 has 128 max dram width (4 channels x 32 bits per channel) * 1 dram clock cycle provides 128*2 bits = 32 bytes * (i.e) 2 dram clocks provides 1 atom * so 2*256=512 dram clocks needed for 256 atoms * W = 512 */ nvidia,count_weight = <0x200>; nvidia,max_dram_channels = /bits/ 8 <4>; nvidia,type = <1>; status = "disabled"; }; }; };