/*
 * arch/arm64/boot/dts/tegra186-cpus-2D4A.dtsi
 *
 * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 */

#include "tegra186-a57-cpuidle.dtsi"
#include "tegra186-denver-cpuidle.dtsi"

/ {
	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&denver_0>;
				};
				core1 {
					cpu = <&denver_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu_a57_0>;
				};
				core1 {
					cpu = <&cpu_a57_1>;
				};
				core2 {
					cpu = <&cpu_a57_2>;
				};
				core3 {
					cpu = <&cpu_a57_3>;
				};
			};
		};

		denver_0: cpu@0 {
			device_type = "cpu";
			compatible = "nvidia,denver", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&DENVER_C6 &DENVER_C7>;
			cpu-ipc = <1024>;
			next-level-cache = <&L2_DENVER>;
			capacity-dmips-mhz = <1024>;
			sched-energy-costs = <&CPU_COST_DENVER &CPU_COST_DENVER>;
		};

		denver_1: cpu@1 {
			device_type = "cpu";
			compatible = "nvidia,denver", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			cpu-idle-states = <&DENVER_C6 &DENVER_C7>;
			cpu-ipc = <1024>;
			next-level-cache = <&L2_DENVER>;
			capacity-dmips-mhz = <1024>;
			sched-energy-costs = <&CPU_COST_DENVER &CPU_COST_DENVER>;
		};

		cpu_a57_0: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57-64bit", "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&A57_C7>;
			cpu-ipc = <752>;
			next-level-cache = <&L2_A57>;
			capacity-dmips-mhz = <752>;
			sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
		};

		cpu_a57_1: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57-64bit", "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "psci";
			cpu-idle-states = <&A57_C7>;
			cpu-ipc = <752>;
			next-level-cache = <&L2_A57>;
			capacity-dmips-mhz = <752>;
			sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
		};

		cpu_a57_2: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a57-64bit", "arm,armv8";
			reg = <0x0 0x102>;
			enable-method = "psci";
			cpu-idle-states = <&A57_C7>;
			cpu-ipc = <752>;
			next-level-cache = <&L2_A57>;
			capacity-dmips-mhz = <752>;
			sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
		};

		cpu_a57_3: cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-a57-64bit", "arm,armv8";
			reg = <0x0 0x103>;
			enable-method = "psci";
			cpu-idle-states = <&A57_C7>;
			cpu-ipc = <752>;
			next-level-cache = <&L2_A57>;
			capacity-dmips-mhz = <752>;
			sched-energy-costs = <&CPU_COST_A57 &CPU_COST_A57>;
		};

		L2_A57: l2-cache0 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
		};

		L2_DENVER: l2-cache1 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
		};
	};

	arm-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 320 0x4>,
			     <0 321 0x4>,
			     <0 296 0x4>,
			     <0 297 0x4>,
			     <0 298 0x4>,
			     <0 299 0x4>;
		interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
				      &{/cpus/cpu@2} &{/cpus/cpu@3}
				      &{/cpus/cpu@4} &{/cpus/cpu@5}>;
	};

	denver-pmu {
		compatible = "nvidia,denver15-pmu";
		interrupts = <0 290 0x4>;
		interrupt-affinity = <&{/cpus/cpu@0}>;
	};

	#include "tegra186-cpus-energy-2D4A.dtsi"
};